Results 61 to 70 of about 41,111,468 (182)

High-Speed CMOS Synchronous Binary Counter With Constant Counting Rate

IEEE Access
In VLSI design, the counter stands as one of the most fundamental and widely utilized components. It finds extensive applications across various fields, including analog-to-digital converters, time-to-digital converters, frequency dividers, phase-locked ...
Sungho Kim, Jeongmin Kim, In-Cheol Park
doaj   +1 more source

Electronic marker for experimental estimation of rotor current delay in an induction motor

Известия высших учебных заведений: Проблемы энергетики
RELEVANCE. In subordinate and field-oriented control of induction motor drives, rotor electromagnetic inertia is often treated implicitly. However, when the bandwidth of inner current loops is increased, rotor dynamics introduces a measurable delay and ...
Maksim M. Golovin, Nikolay N. Portnyagin
doaj   +1 more source

Characterization of digital phase-locked loops [PDF]

, 2003
Phase-locked loops are a relatively new class of circuits used primarily in communication applications. The capture range of a phase-locked loop is a critical parameter because it trades directly with the loop bandwidth.
Vepa, Sri Kiran V S
core  

Phase-Locked Loops for Wireless Communications Digital, Analog and Optical Implementations

, 2002
Phase-Locked Loops for Wireless Communications: Digitial, Analog and Optical Implementations, Second Edition presents a complete tutorial of phase-locked loops from analog implementations to digital and optical designs.
Stephens, Donald R.
core   +1 more source

Experiments with coupled phase locked loops

, 2019
In this paper the experiments with two or more mutually coupled phase locked loops (PLL) are described. The different types of coupled PLLs are simulated and results are confirmed by measuring in real systems.
Štork, Milan, Milan Stork
core   +1 more source

Phase-Locked Loops for Wireless Communications

, 1998
This book is intended for the graduate or advanced undergraduate engineer. The primary motivation for writing the text was to present a complete tutorial of phase-locked loops with a consistent notation.
Donald R. Stephens, Stephens, Donald R.
core   +1 more source

Method of implementing digital phase-locked loops [PDF]

, 1993
In a new formulation for digital phase-locked loops, loop-filter constants are determined from loop roots that can each be selectively placed in the s-plane on the basis of a new set of parameters, each with simple and direct physical meaning in terms of
Stephens, Scott A., Thomas, Jess Brooks, Jr.   +1 more
core  

A 10 mW 3.2 GHz All-Digital Fractional-N PLL Achieving −120-dBc/Hz In-Band Phase Noise Using a Continuous Time Bandpass Delta–Sigma Time-to-Digital Converter in 180-nm CMOS

IEEE Access
This paper presents a continuous-time bandpass delta-sigma time-to-digital converter (CT-BP $\Delta \Sigma $ TDC) for all-digital fractional- $N$ phase-locked loops (ADPLLs) operating under low reference frequency and wide loop bandwidth constraints ...
Thi Viet Ha Nguyen, Cong-Kha Pham
doaj   +1 more source

Method of Implementing Digital Phase-Locked Loops [PDF]

, 1997
In a new formulation for digital phase-locked loops, loop-filter constants are determined from loop roots that can each be selectively placed in the s-plane on the basis of a new set of parameters, each with simple and direct physical meaning in terms of
Stephens, Scott A., Thomas, J. Brooks
core  

Quantization effects in All-Digital Phase-Locked Loops

, 2007
This brief analyzes the impact of the quantization noise sources in all-digital phase-locked loops (ADPLLs), recently employed as frequency synthesizers.
LEVANTINO, SALVATORE, LACAITA, ANDREA LEONARDO, M. Zanuso, SAMORI, CARLO, P. Madoglio   +4 more
core   +1 more source