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A survey of digital phase-locked loops
Proceedings of the IEEE, 1981The purpose of this paper is to present a systematic survey of the theoretical/experimental work accomplished in the area of digital phase-locked loops (DPLL's) during the period of 1960 to 1980. The DPLL represents the heart of the Building blocks required in the implementation of coherent (all digital) communications and tracking receivers.
W.C. Lindsey, null Chak Ming Chie
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Phase-domain all-digital phase-locked loop
IEEE Transactions on Circuits and Systems II: Express Briefs, 2005A fully digital frequency synthesizer for RF wireless applications has recently been proposed. At its foundation lies a digitally controlled oscillator that deliberately avoids any analog tuning controls. When implemented in a digital deep-submicrometer CMOS process, the proposed architecture appears more advantageous over conventional charge-pump ...
R.B. Staszewski, P.T. Balsara
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A Digital BIST for Phase-Locked Loops
2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems, 2008This paper presents a conceptual implementation of a jitter measurement circuit with several BIST (built-in self test) features for embedded phase-locked loops. We demonstrate a fully functional jitter measurement circuit capable of detecting cycle-to-cycle jitter.
Kevin Sliech, Martin Margala
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Digital phase-locked loop with jitter bounded
IEEE Transactions on Circuits and Systems, 1989A design of an all-digital phase-locked loop (DPLL) with direct frequency synthesis is proposed for generating signals that satisfy preimposed requirements on jitter over any given range of frequencies. Control of the jitter is obtained by means of a frequency-phase window comparator which compares the bit overflow/underflow of the direct synthesis ...
S.M. Walters, T. Troudet
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Unbiased Finite-Memory Digital Phase-Locked Loop
IEEE Transactions on Circuits and Systems II: Express Briefs, 2016Digital phase-locked loops (DPLLs) have been commonly used to estimate phase information. However, they exhibit poor performance or, occasionally, a divergence phenomenon, if noise information is incorrect or if there are quantization effects. To overcome the weaknesses of existing DPLLs, we propose a new DPLL with a finite-memory structure called the ...
You, S. +4 more
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Fractional-Order Digital Phase-Locked Loop
2007 14th IEEE International Conference on Electronics, Circuits and Systems, 2007A fractional-order digital phase-locked loop (FODPLL) is proposed. The FODPLL model is developed by approximating a fractional-order digital controlled-oscillator (FODCO) with a finite dimensional discrete transfer function. The design of FODPLLs model is simplified where one only needs to design a FODCO.
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A New DSP Digital Phase Locked Loop
IETE Journal of Research, 1993A new type of digital signal processing type digital phase locked loop is presented. It consists of a second order DPLL and first order DPLL both of which possess an additional automatic-frequency-...
B N Biswas +4 more
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On Optimum Digital Phase-Locked Loops
IEEE Transactions on Communications, 1968This paper gives the design procedure of optimum digital filters for analog-digital phase-locked loops. The inputs considered are the step and ramp change in phase. The digital filters can easily be realized on the digital computer or otherwise. Design curves are given to choose proper noise bandwidth, sampling period, and loop parameters.
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A digital loop filter for a Phase Locked Loop
2011 17th International Conference on Digital Signal Processing (DSP), 2011Modern digital telecommunication and audio systems include a Digital Phase Locked Loop (D-PLL) in a form of a device or an algorithm. Wireless infrastructure, broadband wire-line networks and high end audio systems require very high performance PLLs.
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