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Quantization Effects in All-Digital Phase-Locked Loops
IEEE Transactions on Circuits and Systems II: Express Briefs, 2007 This brief analyzes the impact of the quantization noise sources in all-digital phase-locked loops (ADPLLs), recently employed as frequency synthesizers. In general, the in-band phase noise is not only caused by the phase quantization of the time-to-digital converter, but also by the frequency quantization of the digitally controlled oscillator (DCO ...
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Quasi-Optimum Digital Phase-Locked Loops
IRE Transactions on Communications Systems, 1973Quasi-optimum digital phase-locked loops (DPLL) are derived utilizing nonlinear estimation theory. Nonlinear approximations are employed to yield realizable loop structures. Baseband equivalent loop gains are derived, which, under high signal-to-noise ratio conditions may be calculated off line.
Darryl R. Polk, Someshwar C. Gupta
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A survey of digital phase-locked loops
Proceedings of the IEEE, 1981The purpose of this paper is to present a systematic survey of the theoretical/experimental work accomplished in the area of digital phase-locked loops (DPLL's) during the period of 1960 to 1980. The DPLL represents the heart of the Building blocks required in the implementation of coherent (all digital) communications and tracking receivers.
W C Lindsey
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On Optimum Digital Phase-Locked Loops
IRE Transactions on Communications Systems, 1968This paper gives the design procedure of optimum digital filters for analog-digital phase-locked loops. The inputs considered are the step and ramp change in phase. The digital filters can easily be realized on the digital computer or otherwise. Design curves are given to choose proper noise bandwidth, sampling period, and loop parameters.
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ICASSP '78. IEEE International Conference on Acoustics, Speech, and Signal Processing, 2005
This paper deals with the design, construction and evaluation of a Digital Phase-Locked Loop. An exclusive OR gate serves as a linear phase detector. The integrator consists of a cascade of up/down decade counters. The D.C. value of each cycle from the phase detector is measured and accumulated. The rate of integration is determined by the clock input.
C. P. Reddy, Erik Fountain
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This paper deals with the design, construction and evaluation of a Digital Phase-Locked Loop. An exclusive OR gate serves as a linear phase detector. The integrator consists of a cascade of up/down decade counters. The D.C. value of each cycle from the phase detector is measured and accumulated. The rate of integration is determined by the clock input.
C. P. Reddy, Erik Fountain
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A Fast-Locking Digital Phase-Locked Loop
Third International Conference on Information Technology: New Generations (ITNG'06), 2006A conventional digital phase-locked loop (DPLL) is designed using (Baker et al., 2003) to operate at 1GHz using 0.18 mum CMOS technology; its lock time is 4.19 mus. By adding a coarse/fine tuning control unit composed of a digital-to-analog converter (DAC) and a counter as well as switching the currents of the charge pump, a fast-locking DPLL results ...
Mahmoud Fawzy Wagdy, Srishti Vaishnava
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A Digital BIST for Phase-Locked Loops
2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems, 2008This paper presents a conceptual implementation of a jitter measurement circuit with several BIST (built-in self test) features for embedded phase-locked loops. We demonstrate a fully functional jitter measurement circuit capable of detecting cycle-to-cycle jitter.
Kevin Sliech, Martin Margala
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