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2022
This thesis was scanned from the print manuscript for digital preservation and is copyright the author. Researchers can access this thesis by asking their local university, institution or public library to make a request on their behalf. Monash staff and postgraduate students can use the link in the References field.
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This thesis was scanned from the print manuscript for digital preservation and is copyright the author. Researchers can access this thesis by asking their local university, institution or public library to make a request on their behalf. Monash staff and postgraduate students can use the link in the References field.
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Nonlinear dynamics of a digital phase locked loop
IEEE Transactions on Communications, 1989A second-order digital phase-locked loop may exhibit unusual behavior for some parameters due to a fractal boundary between the basin of attraction of the locked fixed point and the attracting basins of coexisting periodic orbits. The usual optimization criterion of the loop parameters using linearized analysis is insufficient, due to coexisting ...
Greg M. Bernstein +2 more
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First-Order Digital Phase Lock Loop with Continuous Locking
2013 Fifth International Conference on Computational Intelligence, Communication Systems and Networks, 2013A zero-crossing digital phase locked loop (ZCDPLL) system with dual gain selection technique for fast acquisition, reliable locking and improved phase noise and jitter performance is proposed. The system is designed and simulated based on adaptive loop gain techniques.
Saleh R. Al-Araji +2 more
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A Novel Fast-Lock-in Digitally Controlled Phase-Locked Loop
IEICE Transactions on Electronics, 2008A novel fast lock-in digitally controlled phase-locked loop (DCPLL) is proposed in this letter. This DCPLL adopts a novel frequency search algorithm to reduce the lock-in time. Furthermore, to reduce the power consumption, the frequency divider is reused as a frequency detector during the frequency acquisition, and reused as a time-to-digital converter
Xin Chen 0039 +2 more
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A Novel Flash Fast-Locking Digital Phase-Locked Loop
2009 Sixth International Conference on Information Technology: New Generations, 2009A FLASH digital phase-locked loop (DPLL) is designed using 0.18μm CMOS process and a 3.3V power supply. It operates in the frequency range 200MHz – 2GHz. The DPLL operation includes two stages: (1) a novel coarse-tuning stage based on a flash algorithm similar to the algorithm employed in flash A/D converters, and (2) a fine-tuning stage similar to ...
Mahmoud Fawzy Wagdy +1 more
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Fractional-Order Digital Phase-Locked Loop
2007 14th IEEE International Conference on Electronics, Circuits and Systems, 2007A fractional-order digital phase-locked loop (FODPLL) is proposed. The FODPLL model is developed by approximating a fractional-order digital controlled-oscillator (FODCO) with a finite dimensional discrete transfer function. The design of FODPLLs model is simplified where one only needs to design a FODCO.
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A digital phase‐locked loop with and filter
Electronics and Communications in Japan (Part I: Communications), 1980AbstractIn general, it is known that if the stationary characteristics of a PPL, phase‐locked loop, are improved, its transient response characteristics are deteriorated, while if the transient response characteristics are improved, its stationary characteristics are deteriorated.
Taiichiro Kurita +3 more
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The stationary phase error distribution of a digital phase-locked loop
IEEE Transactions on Communications, 2000The stationary properties of a first-order digital phase-locked loop based on the extended Kalman filter (EKF-PLL) are investigated. A discrete Markov chain approximation of the phase error process is used to derive the asymptotic distribution of the phase error as well as the distribution of the time at which the EKF-PLL is first "out of lock", given ...
Glen Skiller, Dawei Huang
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A Fast-Locking All-Digital Phase-Locked Loop With Dynamic Loop Bandwidth Adjustment
IEEE Transactions on Circuits and Systems I: Regular Papers, 2015A fast-locking all-digital phase-locked loop (ADPLL) including a fast-locking unit, a multi-level bang-bang phase detector (ML-BBPD), a dynamic gain adjustment controller (DGAC), and a digitally controlled oscillator (DCO) is presented. The ML-BBPD provides multi-level outputs with different phase errors.
Jung-Mao Lin, Ching-Yuan Yang
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Comparison and Simulation of Analog and Digital Phase Locked Loop
2018 9th International Conference on Computing, Communication and Networking Technologies (ICCCNT), 2018This paper presents a comparative study between the two basic types of Phase locked loop (PLL) i.e. Analog phase locked loop (APLL) and Digital Phase locked loop (DPLL) and their implementation in Simulink. It has been observed that different types of PLL have different performance parameters and response time.
Abhishek Godave +2 more
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