Results 231 to 240 of about 2,839 (257)
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STABILITY OF SYNCHRONIZATION IN NETWORKS OF DIGITAL PHASE-LOCKED LOOPS
International Journal of Bifurcation and Chaos, 1995We analyze the linear stability of the synchronized state in networks of N identical digital phase-locked loops. These are pulse-coupled oscillator arrays in which the frequency (rather than the phase) of each oscillator is updated discontinuously whenever that oscillator reaches a specific phase in its cycle.
Goldsztein, Guillermo +1 more
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Unbiased Finite-Memory Digital Phase-Locked Loop
IEEE Transactions on Circuits and Systems II: Express Briefs, 2016Digital phase-locked loops (DPLLs) have been commonly used to estimate phase information. However, they exhibit poor performance or, occasionally, a divergence phenomenon, if noise information is incorrect or if there are quantization effects. To overcome the weaknesses of existing DPLLs, we propose a new DPLL with a finite-memory structure called the ...
Sung Hyun You +4 more
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On the Performance of Digital Phase Locked Loops in the Threshold Region
IEEE Transactions on Communications, 1974Extended Kalman filter algorithms are used to obtain a digital phase lock loop structure for demodulation of angle modulated signals. It is shown that the error variance equations obtained directly from this structure enable one to predict threshold if one retains higher frequency terms.
G. T. Hurst, S. C. Gupta
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Quantizing and Sampling Considerations in Digital Phased-Locked Loops
IEEE Transactions on Communications, 1974Quantization and sampling effects on the digital phasedlocked loop (DPLL) structures obtained for demodulation of anglemodulated signals using extended Kalman filter algorithms are investigated for the high signal-to-noise ratio (SNR) case in this paper. First, the problem of quantization is considered.
Gorman Thomas Hurst, Someshwar C. Gupta
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All Digital Phase-Locked Loops
1998In this chapter, we are going to extend our survey to loops that have do not have analog prototypes. Lindsey and Chie [1] performed a 1981 survey of digital PLLs that is recommended to the reader desiring additional architectures.
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IEEE Transactions on Circuits and Systems Part 2: Express Briefs, 2007
Pavan Kumar Hanumolu +2 more
exaly
Pavan Kumar Hanumolu +2 more
exaly
A Hardened-by-Design Technique for RF Digital Phase-Locked Loops
IEEE Transactions on Nuclear Science, 2006T D Loveless, L W Massengill, B L Bhuva
exaly

