Results 41 to 50 of about 1,070 (143)

Push–pull mode digital control for LLC series resonant dc‐to‐dc converters

IET Power Electronics, Volume 8, Issue 11, Page 2115-2124, November 2015., 2015
This study presents the design and performance evaluation of the digital control adapted to an LLC series resonant dc‐to‐dc converter operating with wide input and load variations. The proposed control design correctly incorporates the wide‐varying power stage dynamics and variable small‐signal gain of a digitally controlled oscillator, thereby ...
Syam K. Pidaparthy, Jinhaeng Jang, Byungcho Choi   +2 more
wiley   +1 more source

Synchronized State in Networks of Digital Phase-Locked Loops [PDF]

, 2010
International audienceClock distribution networks of synchronized oscillators are an alternative approach to classical tree-like clock distribution methods.
Akre, Jean-Michel, Colinet, Eric, Galayko, Dimitri, Juillard, Jérôme   +3 more
core   +3 more sources

Design of an All‐Digital Synchronized Frequency Multiplier Based on a Dual‐Loop (D/FLL) Architecture

VLSI Design, Volume 2012, Issue 1, 2012., 2012
This paper presents a new architecture for a synchronized frequency multiplier circuit. The proposed architecture is an all‐digital dual‐loop delay‐ and frequency‐locked loops circuit, which has several advantages, namely, it does not have the jitter accumulation issue that is normally encountered in PLL and can be adapted easily for different FPGA ...
Maher Assaad, Mohammed H. Alser, Antonio G. M. Strollo   +2 more
wiley   +1 more source

RGB‐Single‐Chip OLEDs for High‐Speed Visible‐Light Communication by Wavelength‐Division Multiplexing

Advanced Science, Volume 11, Issue 47, December 18, 2024.
High‐speed red, green, and blue organic light‐emitting diodes (RGB‐OLEDs) are integrated onto a single substrate and achieve a record data transmission rate for an OLED transmitter system of 3.2 Gbps by exploiting wavelength‐division multiplexing. It is demonstrated that integrating RGB pixels is a useful way to increase the data transmission rate of ...
Kou Yoshida, Cheng Chen, Harald Haas, Graham A. Turnbull, Ifor D. W. Samuel   +4 more
wiley   +1 more source

Semidigital PLL Design for Low‐Cost Low‐Power Clock Generation

Journal of Electrical and Computer Engineering, Volume 2011, Issue 1, 2011., 2011
This paper describes recent semidigital architectures of the phase‐locked loop (PLL) systems for low‐cost low‐power clock generation. With the absence of the time‐to‐digital converter (TDC), the semi‐digital PLL (SDPLL) enables low‐power linear phase detection and does not necessarily require advanced CMOS technology while maintaining a technology ...
Ni Xu, Woogeun Rhee, Zhihua Wang, Sudhakar Pamarti   +3 more
wiley   +1 more source

Metastability-Containing Circuits [PDF]

, 2016
In digital circuits, metastability can cause deteriorated signals that neither are logical 0 or logical 1, breaking the abstraction of Boolean logic. Unfortunately, any way of reading a signal from an unsynchronized clock domain or performing an analog ...
Friedrichs, Stephan, Függer, Matthias, Lenzen, Christoph   +2 more
core   +4 more sources

The Effect of Intermittent Signal on the Performance of Code Tracking Loop in GNSS Receivers

Journal of Electrical and Computer Engineering, Volume 2011, Issue 1, 2011., 2011
This paper analyzes the code tracking performance in the presence of signal blanking in Global Navigation Satellite System (GNSS). The blanking effect is usually caused by buildings that obscure the signal in either a periodic or random manner. In some cases, ideal blanking is used to remove random or periodic interference.
Chung-Liang Chang, Tzi-Dar Chiueh
wiley   +1 more source

A Design Approach for Networks of Self-Sampled All-Digital Phase-Locked Loops [PDF]

, 2011
International audienceThis paper addresses the problem of the stability and the performance analysis of N-nodes Cartesian networks of self-sampled all digital phase-locked loops.
Akré, Jean-Michel, Colinet, Eric, Galayko, Dimitri, Javidan, Mohammad, Juillard, Jérôme, Korniienko, Anton, Zianbetov, Eldar   +6 more
core   +3 more sources

Open‐Loop Wide‐Bandwidth Phase Modulation Techniques

Journal of Electrical and Computer Engineering, Volume 2011, Issue 1, 2011., 2011
The ever‐increasing growth in the bandwidth of wireless communication channels requires the transmitter to be wide‐bandwidth and power‐efficient. Polar and outphasing transmitter topologies are two promising candidates for such applications, in future. Both these architectures require a wide‐bandwidth phase modulator.
Nitin Nidhi, Pin-En Su, Sudhakar Pamarti, Kenichi Okada   +3 more
wiley   +1 more source

Design and VHDL Modeling of All-Digital PLLs [PDF]

, 2010
International audienceIn this paper, a VHDL model of a second-order alldigital phase-locked loop (ADPLL) based on bang-bang phase detectors is presented.
Anceau, François, Colinet, Eric, Galayko, Dimitri, Javidan, Mohammad, Juillard, Jérôme, Zianbetov, Eldar   +5 more
core   +3 more sources