Results 161 to 170 of about 688 (209)
High Resolution FPGA DPWM Based on Variable Clock Phase Shifting [PDF]
IEEE Transactions on Power Electronics, 2010 This paper proposes a very high resolution DPWM architecture that takes advantage of an FPGA advanced clock management capability: the fine phase shifting of the clock. This feature is available in almost every FPGA nowadays, allowing very small and programmable delays between the input and output clocks.
Angel De Castro, Elias Todorovich
exaly +5 more sources
Triangle Carrier-Based DPWM for Three-Level NPC Inverters [PDF]
IEEE Journal of Emerging and Selected Topics in Power Electronics, 2018 This paper proposes a triangle carrier-based discontinuous pulsewidth modulation (TCB-DPWM) implement method for three-level neutral-point-clamped (3L-NPC) inverters.
Kai Li, Min Wei, Chuan Xie
exaly +2 more sources
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Time-Domain Analysis of Sampling Effect in DPWM of DC–DC Converters
IEEE Transactions on Industrial Electronics, 2015This paper investigates time-domain analysis of sampling effect in digital pulsewidth modulation (DPWM) of dc–dc converters. The relation between the sampling delay, duty ratio, and multisampling factor (sampling to carrier frequency ratio) has been characterized.
Mayank Kumar, Rajesh Gupta
exaly +2 more sources
Reduction of Motor Acoustic Noise with Rampwise DPWM
2020 23rd International Conference on Electrical Machines and Systems (ICEMS), 2020The discontinuous PWM method is widely used because the switching loss can be drastically reduced. However, acoustic noise generated from a motor and a reactor with the discontinuous PWM method increases more than with the conventional sinusoidal PWM method.
Hideki Ayano +4 more
openaire +1 more source
High Speed DPWM for Digital Power Converter Controller
2019 42nd International Convention on Information and Communication Technology, Electronics and Microelectronics (MIPRO), 2019This study proposes a new architecture of digital pulse width modulator (DPWM) for power converter with digital control loop. The described architecture is based on a new counter-based concept. The new approach requires two counter loops: a slow big one and a fast small one.
Y. Smirnov +3 more
openaire +1 more source
Effects on Capacitor Lifetime of DPWM Method for Vienna Rectifier
2019 IEEE 4th International Future Energy Electronics Conference (IFEEC), 2019The effect of a capacitor on the overall system loss may not be critical, but a capacitor is an essential component in terms of overall system life. In this investigation, we analyzed the influence of the pulse width modulation method for a Vienna rectifier on the capacitor lifetime.
Il-Seob Kwon +3 more
openaire +1 more source
Implementation of the ISPWM-DPWM-S2 technique on a microcontroller
International Symposium on Signals, Circuits and Systems ISSCS2013, 2013In this paper, we implemented on a microcontroller a modified-wave reference signal (DPWM-S2) modulated by an Inverted Sine Pulse Width Modulation (ISPWM). The microcontroller commands a three-phase asynchronous motor by means of a three-phase inverter.
C. Aghion +3 more
openaire +1 more source