Results 171 to 180 of about 688 (209)

Hybrid DPWM with Digital Delay-Locked Loop

2006 IEEE Workshops on Computers in Power Electronics, 2006
This paper introduces a fully synthesizable hybrid digital pulse width modulator (DPWM). The DPWM includes a digital delay locked loop around a delay-line with discretely programmable delay cells to achieve constant-frequency clocked operation with the best possible resolution over a range of process or temperature variations.
Vahid Yousefzadeh, Toru Takayama, Dragan Maksimovi   +2 more
openaire   +1 more source

Design and implementation of sigma-delta DPWM controller for switching converter

2009 IEEE International Symposium on Circuits and Systems, 2009
This paper describes the complete design and implementation of a low-power sigma-delta DPWM (Σ-Δ DPWM) controller for switching converter which can operate at a very high frequency. In the previous design approach, the effective resolution of Σ-Δ DPWM, i.e.
Pui-Kei Leong, Chun-Hung Yang, Chi-Wai Leng, Chien-Hung Tsai   +3 more
openaire   +1 more source

Hybrid DPWM implementation using coarse and fine programmable ADLL

Microelectronics Journal, 2014
abstract In the paper we propose a novel architecture and implementation of 11-bit Digital Pulse WidthModulator (DPWM) circuit based on previously known building blocks. Linearized Class-AD Double-sided (LADD) algorithm has been used to calculate the DPWM signals of the 11-bit resolution hybridDPWM for a Class-AD digital audio amplifier.
Jacek Jasielski, Stanislaw W. Kuta, Witold Machowski, Wojciech Kolodziejski   +3 more
openaire   +1 more source

Low-Power Counter-Based Delay Line Design For DPWM

2019 IEEE International Conference on Consumer Electronics - Taiwan (ICCE-TW), 2019
An efficient low-power counter-based digital pulse width modulation (DPWM) is presented. The architecture design has a bi-direction counter, delay cells and multiplexers. If the delay cells are unselected, they will be gated the clock input to stop their operations.
Cheng-Jie Yang, Ming-Jie Li, Chen-Yueh Liu, Ming-Hwa Sheu, Chi-Chia Sun   +4 more
openaire   +1 more source

DC-Link Capacitor-Current Ripple Reduction in DPWM-Based Back-to-Back Converters

IEEE Transactions on Industrial Electronics, 2018
This paper proposes an improved offset selection method for discontinuous-pulse-width-modulation (DPWM)-based back-to-back converters to reduce dc-link current ripple. DPWM is introduced to power converters to diminish the stress on power transistors and prolong their lifespan.
Anatolii Tcai, Kyo-Beum Lee
exaly   +2 more sources

A Hybrid DPWM for Vienna Rectifiers Based on the Three-Level to Two-Level Conversion

IEEE Transactions on Industrial Electronics, 2022
In view of the large neutral-point (NP) voltage fluctuation and the high low-frequency harmonics in the input current of conventional discontinuous PWM for the Vienna rectifier, a hybrid discontinuous PWM (HDPWM) is proposed based on the three-level to two-level conversion. The proposed HDPWM combines the modulation degree of freedom, namely the vector
Zhou He, Hongfa Ding, Zibo Chen, Qi Zhao, Zhuyu Xun, Dandi Zhang, Jiannan Shao   +6 more
openaire   +1 more source

FPGA-based high resolution DPWM control circuit [PDF]

Journal of Systems Engineering and Electronics, 2018
exaly   +2 more sources

DPWM-S3 software control for three-phase inverters

2009 International Symposium on Signals, Circuits and Systems, 2009
In this paper we describe a DPWM-S3 software control method implemented on a microcontroller. This technique was tested by simulations and in practice on a three-phase inverter with an AC motor (0.37KW) as output load.
Cristian Aghion, Mihai Lucanu, Ovidiu Ursaru   +2 more
openaire   +1 more source

Design of a Counter-Based DPWM Using RC Charge

2014 International Symposium on Computer, Consumer and Control, 2014
Conventional counter-based digital PWM (DPWM) has simple hardware architecture to generate the PWM pulse, however, the resolution of the counter-based DPWM is directly proportional to its input reference clock, and thus the higher clock frequency is required, which means higher dynamic power consumption and noise interference may be incurred.
exaly   +2 more sources

CMOS bridge rectifier boost converter with internal ASIC DPWM

2016 IEEE Asia-Pacific Conference on Applied Electromagnetics (APACE), 2016
This paper presents the Application Specific Integrated Circuit (ASIC) design of a Digital Pulse Width Modulation (DPWM) signal generator, for the implementation of PWM control signal generator, to be integrated on a single die with the single-stage input-powered bridge rectifier with boost switch (BRBS) DC boost converter, in view to eliminate the ...
Mohd Asyraf Rongi, Mohd Khairul Mohd Salleh, Emilia Noorsal, Roskhatijah Radzuan, Abdul Karimi Halim   +4 more
openaire   +1 more source