Results 111 to 114 of about 604 (114)

DRAM-Latency Optimization Inspired by Relationship between Row-Access Time and Refresh Timing

IEEE Transactions on Computers, 2016
Lee-Sup Kim, Jungwhan Choi, Jaemin Jang   +2 more
exaly  

Cached DRAM for ILP processor memory access latency reduction

IEEE Micro, 2001
exaly  

Sectored DRAM: A Practical Energy-Efficient and High-Performance Fine-Grained DRAM Architecture

Transactions on Architecture and Code Optimization
Ataberk Olgun, Onur Mutlu, F Nisa Bostanci   +2 more
exaly  

DRAM errors in the wild

Performance Evaluation Review, 2009
exaly