Results 101 to 110 of about 604 (114)
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What Your DRAM Power Models Are Not Telling You

Proceedings of the ACM on Measurement and Analysis of Computing Systems, 2018
Niladrish Chatterjee   +2 more
exaly  

DRAM Refresh Mechanisms, Penalties, and Trade-Offs

IEEE Transactions on Computers, 2016
Bruce Jacob
exaly  

Ramulator: A Fast and Extensible DRAM Simulator

IEEE Computer Architecture Letters, 2016
Onur Mutlu, Yoongu Kim
exaly  

Trends in the development of ULSI DRAM capacitors

Integrated Ferroelectrics, 1994
exaly  

Assessing merged DRAM/Logic technology

The Integration VLSI Journal, 1999
Tom Chen
exaly  

Design-Induced Latency Variation in Modern DRAM Chips

Proceedings of the ACM on Measurement and Analysis of Computing Systems, 2017
Onur Mutlu   +2 more
exaly  

Applying PSO-based BPN for predicting the yield rate of DRAM modules produced using defective ICs

International Journal of Advanced Manufacturing Technology, 2009
Zne-Jung Lee   +2 more
exaly  

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