Results 121 to 130 of about 18,499 (235)

A FAST SYNCHRONOUS PIPELINED DRAM (SP-DRAM) ARCHITECTURE WITH SRAM BUFFERS

, 2020
We propose a Synchronous Pipelined DRAM (SP ...

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DRAM energy reduction by prefetching-based memory traffic clustering

, 2011
DRAMs consume a large portion of total system energy consumption. Thus, reducing DRAM energy consumption is able to prolong the lifetime of battery-operated embedded/portable systems.
Yebin Lee, Lee, Yebin, Soontae Kim, Kim, Soontae   +3 more
core   +1 more source

Nonlinear Variation Decomposition of Neural Networks for Holistic Semiconductor Process Monitoring

Advanced Intelligent Systems
Artificial intelligence (AI) is increasingly used to solve multi‐objective problems and reduce the turnaround times of semiconductor processes. However, only brief AI explanations are available for process/device/circuit engineers to provide holistic ...
Hyeok Yun, Hyundong Jang, Seunghwan Lee, Junjong Lee, Kyeongrae Cho, Seungjoon Eom, Soomin Kim, Choong‐Ki Kim, Hong‐Chul Byun, Seongjoo Han, Min‐Soo Yoo, Rock‐Hyun Baek   +11 more
doaj   +1 more source

Dram shop insurance

, 2007
Title from Web page (viewed Dec. 26, 2007).; "December 17, 2007."; Discusses dram shop laws in New England and whether any state requires its liquor licensees to carry dram shop insurance.; Harvested from the web on 12/29 ...
Duffy, Daniel, 1951-
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Design a DRAM backend for the impulse memory system [PDF]

, 2000
technical reportThe Impulse Adaptable Memory System is a new memory system that exposes DRAM access patterns not seen in conventional memory systems.
Zhang, Lixin
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dram-shops

, 1970
dram-shop. . . to lay up against the day of adversity, and for the support of their families, those sums which are now so improvidently squandered in the dram-shops to the ruin, but too often, I fear, of both soul and body.

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Enabling Efficient and Scalable DRAM Read Disturbance Mitigation via New Experimental Insights into Modern DRAM Chips

Increasing storage density exacerbates DRAM read disturbance, a circuit-level vulnerability exploited by system-level attacks. Unfortunately, existing defenses are either ineffective or prohibitively expensive.
Yağlıkçı, Abdullah Giray
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SCALE DRAM Subsystem Power Analysis

, 2005
To address the needs of the next generation of low-power systems, DDR2 SDRAM offers a number of low-power modes with various performance and power consumption tradeoffs. The SCALE DRAM Subsystem is an energy-aware DRAM system with various system policies
Vimal Bhalodia
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Unlocking the performance limits of 2T0C DRAM with Ω-shaped-gated single-crystal In₂O₃ FETs. [PDF]

Sci Adv
Zuo S, Xie Z, Zhao X, Tang L, Zhao Y, Zeng Y, Niu W, Liu S, Li Q, Yang G, Li L, Wei Z, Ye C, Zou X, Liu X, Liao L, He P.   +16 more
europepmc   +1 more source

Flexible-Latency Dram: Understanding and Exploiting Latency Variation in Modern Dram Chips

, 2018
This article summarizes key results of our work on experimental characterization and analysis of latency variation and latency-reliability trade-offs in modern DRAM chips, which was published in SIGMETRICS 2016 [ 24], and examines the work's ...
Lee, Donghyuk, Ghose, Saugata, Hsieh, Kevin, Mutlu, Onur, Hassan, Hasan, Kashyap, Abhijith, Chang, Kevin K.   +6 more
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