Results 1 to 10 of about 23,139 (118)
A Low-Power High-Speed Dynamic Comparator With a Transconductance-Enhanced Latching Stage
IEEE Access, 2019 Low-power, high-speed dynamic comparators are highly desirable in the design of high-speed analog-to-digital converters (ADC) and digital I/O circuits. Most dynamic comparators use a pair of cross-coupled inverters as the latching stage, which provides ...
Yao Wang +5 more
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e-Prime: Advances in Electrical Engineering, Electronics and Energy, 2023 The latched comparator is an essential element found in all analogue-to-digital converter (ADC) architectures. The present study aims to develop a latched comparator with the objective of mitigating kickback noise.
Pradeep Jinka, Ramashri Tirumala
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Design of a High-Speed and Low Power CMOS Comparator for A/D Converters [PDF]
Journal of Electrical and Computer Engineering Innovations, 2021 Background and Objectives: Comparators play a critical role in the analog to digital converters (ADCs) and digital to analog converters (DACs). So, different structures have been proposed to improve their performance.
F. Shakibaee, A. Bijari, S.H. Zahiri
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IET Circuits, Devices and Systems, 2022 In this paper, a latch‐based energy‐efficient dynamic comparator is presented in Carbon Nanotube Field Effect Transistor (CNTFET) technology. The proposed comparator consists of two main stages: pre‐amplifier and latch.
Hamid Mahmoodian +3 more
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Design of high speed and low offset dynamic latch comparator in 0.18 µm CMOS process. [PDF]
PLoS ONE, 2014 The cross-coupled circuit mechanism based dynamic latch comparator is presented in this research. The comparator is designed using differential input stages with regenerative S-R latch to achieve lower offset, lower power, higher speed and higher ...
Labonnah Farzana Rahman +4 more
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Advances in Electrical and Electronic Engineering, 2019 Currently, dynamic comparator approach necessitates in high-speed and power efficient analog-to-digital converter applications due to its high latching speed and ultra-low power consumption. In this paper, a~novel dynamic comparator is proposed to reduce
Vikrant Varshney, Rajendra Kumar Nagaria
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Electronics Letters, 2021 Here, a 4‐level pulse amplitude modulation direct decision feedback equaliser (DFE) with a novel dynamic current‐mode‐logic comparator (DCMLC) is presented.
Dengjie Wang +5 more
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Mokslas: Lietuvos Ateitis, 2016 The article describes the dynamics researches of mechanical system of angle comparator. The goal of research is to determine the stability of mechanical system of angle comparator.
Valdemar Prokopovič +2 more
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An Improved Strong Arm Comparator With Integrated Static Preamplifier
IEEE Access, 2023 This paper presents a novel Strong Arm comparator in which the input pair is reused as a static amplifier to preamplify the input signal during the precharge phase. The proposed approach relaxes the main trade-offs that characterize the Strong Arm latch:
Valerio Spinogatti +4 more
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A 0.15-to-0.5 V Body-Driven Dynamic Comparator with Rail-to-Rail ICMR
Journal of Low Power Electronics and Applications, 2023 In this paper, a novel dynamic body-driven ultra-low voltage (ULV) comparator is presented. The proposed topology takes advantage of the back-gate configuration by driving the input transistors’ gates with a clocked positive feedback loop made of two AND
Riccardo Della Sala +4 more
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