Results 31 to 40 of about 64,742 (346)
A Low-Power High-Speed Dynamic Comparator With a Transconductance-Enhanced Latching Stage
IEEE Access, 2019 Low-power, high-speed dynamic comparators are highly desirable in the design of high-speed analog-to-digital converters (ADC) and digital I/O circuits. Most dynamic comparators use a pair of cross-coupled inverters as the latching stage, which provides ...
Yao Wang +5 more
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Monolithic Si-Based AlGaN/GaN MIS-HEMTs Comparator and Its High Temperature Characteristics
Applied Sciences, 2021 Monolithic GaN High Electron Mobility Transistor (HEMT)-integrated circuits are a promising application of wide band-gap materials. To date, most GaN-based devices behave as NMOS-like transistors. As only NMOS GaN HEMT is currently commercially available,
Fan Li +9 more
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A High-Speed and Low-Offset Dynamic Latch Comparator
The Scientific World Journal, 2014 Circuit intricacy, speed, low-offset voltage, and resolution are essential factors for high-speed applications like analog-to-digital converters (ADCs).
Labonnah Farzana Rahman +4 more
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Dynamics of a Carriage System of Comparator for Calibrating the Line Standards of Length
The Journal of Engineering Research, 2015 This paper presents research dynamic properties of a calibration comparator which is used to calibrate high precision line standards of length. For this purpose, multi-body dynamic and mathematical models of a carriage system of the comparator were ...
A. Kilikevičius +2 more
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IEEE Access, 2021 A 12-bit 80 MS/s hybrid type analog-to-digital converter (ADC) for high sampling speed and low power applications is presented in this paper. It has a subranging architecture with a front end of 6-bit Flash ADC with five channels of 6-bit time ...
Deeksha Verma +11 more
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Introduction: towards dynamic comparative analysis
Anthropology of food, 2014 Comparison is at the heart of social sciences, and the study of ‘other’ culinary cultures is as old as the study of food practices – as a privileged and enduring object of anthropology. More recently, the cross-national comparison of food habits has received a new impulse from other quarters, as the association of eating habits with public health ...
Darmon, Isabelle, Warde, Alan
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A 0.45pJ/conv-step 1.2Gs/s 6b full-Nyquist non-calibrated flash ADC in 45nm CMOS and its scaling behavior [PDF]
, 2009 A 6-bit 1.2 Gs/s non-calibrated flash ADC in a standard 45nm CMOS process, that achieves 0.45pJ/conv-step at full Nyquist bandwidth, is presented. Power efficient operation is achieved by a full optimization of amplifier blocks, and by innovations in the
Annema, Anne-Johan +5 more
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Design of an Efficient Parallel Comparator Architecture for Low Power Delay Product
Advances in Electrical and Electronic Engineering, 2021 A binary comparator architecture is proposed in this work for static logic to achieve both low-power and high-performance operations. It also presents a detailed timing performance and power analysis of various state-of-the-art comparator designs.
Mangal Deep Gupta, Rajeev Kumar Chauhan
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When are comparative dynamics monotone? [PDF]
Review of Economic Dynamics, 2003 Abstract A common problem in dynamic economic theory is to determine when an increase in a parameter and/or an initial condition increases the future dynamics of a theoretical economy. This paper provides conditions that are necessary and sufficient for making statements of this type. The result is applicable to situations with a single agent or with
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Comparing Dynamic Equilibrium Economies to Data [PDF]
SSRN Electronic Journal, 2001 This paper studies the properties of the Bayesian approach to estimation and comparison of dynamic equilibrium economies. Both tasks can be performed even if the models are nonnested, misspecified, and nonlinear. First, the authors show that Bayesian methods have a classical interpretation: asymptotically the parameter point estimates converge to their
Jesús Fernández-Villaverde +1 more
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