Results 231 to 240 of about 131,761 (282)

Parallel Combinational Equivalence Checking

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2020
Combinational equivalence checking (CEC) has been widely applied to ensure design correctness after logic synthesis and technology-dependent optimization in digital integrated circuit design. CEC runtime is often critical for large designs, even when advanced techniques are employed. Three complementary ways for enabling parallelism in CEC are proposed,
Vinicius N. Possani, Alan Mishchenko, Renato P. Ribas, Andre I. Reis   +3 more
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Equivalence checking using abstract BDDs

Proceedings International Conference on Computer Design VLSI in Computers and Processors, 2002
We introduce a new equivalence checking method based on abstract BDDs (aBDDs). The basic idea is the following: given an abstraction function, aBDDs reduce the size of BDDs by merging nodes that have the same abstract value. An aBDD has bounded size and can be constructed without constructing the original BDD.
S Jha, Y Lu, M Minea, Clarke, Edmund M
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Checking equivalence for partial implementations

Proceedings of the 38th conference on Design automation - DAC '01, 2001
We consider the problem of checking whether a partial implementation can (still) be extended to a complete design which is equivalent to a given full specification.Several algorithms trading off accuracy and computational resources are presented: Starting with a simple 0,1,&KHarX-based simulation, which allows approximate solutions, but is not able to
C. Scholl, B. Becker
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Equivalence Checking Benchmark

2022
This is the benchmark of Equivalent and Non-equivalent Java/C programs.
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Data-driven equivalence checking

Proceedings of the 2013 ACM SIGPLAN international conference on Object oriented programming systems languages & applications, 2013
We present a data driven algorithm for equivalence checking of two loops. The algorithm infers simulation relations using data from test runs. Once a candidate simulation relation has been obtained, off-the-shelf SMT solvers are used to check whether the simulation relation actually holds.
Rahul Sharma, Eric Schkufza, Berkeley Churchill, Alex Aiken   +3 more
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Equivalence Checking Using Cuts And Heaps

Proceedings of the 34th Design Automation Conference, 1997
This paper presents a verification technique which isspecifically targeted to formally comparing large combinational circuits with some structural similarities. The approach combines the application of BDDs withcircuit graph hashing, automatic insertion of multiple cut frontiers, and a controlled elimination of false negative verification results ...
Andreas Kuehlmann, Florian Krohm
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Equivalence checking for comparing user interfaces

Proceedings of the 7th ACM SIGCHI Symposium on Engineering Interactive Computing Systems, 2015
Plastic User Interfaces (UIs) have the capacity to adapt tochanges in their context of use while preserving usability.This exposes users to different versions of UIs that can diverge from each other at several levels, which may cause lossof consistency. This raises the question of similarity betweenUIs.
Oliveira, Raquel, Dupuy-Chessa, Sophie, Calvary, Gaëlle   +2 more
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Symbolic equivalence checking

1993
We describe the implementation, within Aldebaran of an algorithmic method allowing the generation of a minimal labeled transition system from an abstract model; this minimality is relative to an equivalence relation. The method relies on a symbolic representation of the state space.
J. C. Fernandez, A. Kerbrat, L. Mounier
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Equivalence Checking of Reversible Circuits

2009 39th International Symposium on Multiple-Valued Logic, 2009
Determining the equivalence of reversible circuits designed to meet a common specification is considered. The circuits' primary inputs and outputs must be in pure logic states but the circuits may include elementary quantum gates in addition to reversible logic gates.
Robert Wille, Daniel Große, D. Michael Miller, Rolf Drechsler   +3 more
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Sequential equivalence checking using cuts

Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005., 2005
This paper presents an algorithm which is an improvement of Van Eijk's algorithm (2000) by incorporating a cutpoints technique (Kuelhmann and Krohm, 1997). Combinational verification often uses the technique to convert large scale circuits to several small ones, which will be verified separately.
Wei Huang, PuShan Tang, Min Ding
openaire   +1 more source