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GMRVGG: A Bearing Fault Diagnosis Method Based on Tri-Modal Image Feature Fusion. [PDF]
Li A, Li Y, Wang X, Yin J.
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ITDFNet: a multi-dimensional fusion image and temporal dual-branch network for bearing fault diagnosis. [PDF]
Cai S, Zhang Y.
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A Hybrid VMD-Transformer-BiLSTM Framework with Cross-Attention Fusion for Aileron Fault Diagnosis in UAVs. [PDF]
Song Y, Zheng W, Zhang X, Guo R.
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Design of a dynamics-based hydraulic controller for lifting manipulator wrist and its stability analysis. [PDF]
Li B.
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Comparative analysis of deep learning algorithms for rolling element bearing fault classification under variable loads and speeds. [PDF]
Vishal P +4 more
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A Dual-Source Evidence-Driven Semi-Supervised Belief Rule Base for Fault Diagnosis. [PDF]
Zhang X, Fan Z, He W, He H.
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Fault Diagnosis and Fault Model Aliasing
IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05), 2005During fault diagnosis, the existence of equivalent faults, or faults that are not distinguished by the test set applied to the circuit, can create ambiguity as to the location of a defect. This happens if the circuit-under-test produces a response that matches the circuit response in the presence of two faults in different locations of the circuit ...
Irith Pomeranz +2 more
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Fault modeling and fault equivalence in CMOS technology
Journal of Electronic Testing, 1991The need for greater reliability in the fault coverage of test sequences for VLSI circuits has led to the proposal for more accurate fault models and test pattern generation tools. Such improvements bring about a large increase in the fault list to be considered and in the CPU time needed to generate the test.
Marie-Lise Flottes +2 more
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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2005
Traditionally, digital testing of integrated semiconductor circuits has focused on manufacturing defects. There is another class of failures that happens due to circuit marginalities. Circuit-marginality failures are on the rise due to shrinking process geometries, diminishing supply voltage, sharper signal-transition rates, and aggressive styles in ...
Kundu, S +3 more
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Traditionally, digital testing of integrated semiconductor circuits has focused on manufacturing defects. There is another class of failures that happens due to circuit marginalities. Circuit-marginality failures are on the rise due to shrinking process geometries, diminishing supply voltage, sharper signal-transition rates, and aggressive styles in ...
Kundu, S +3 more
openaire +2 more sources
EAGE Conference on Petroleum Geostatistics, 2007
Although faults traditionally have been modelled as membrane-like surfaces, the flow pattern through a fault is affected in a volumetric region. The physical properties of the fault rock will be different from what they were prior to the faulting process.
Skorstad, Arne +4 more
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Although faults traditionally have been modelled as membrane-like surfaces, the flow pattern through a fault is affected in a volumetric region. The physical properties of the fault rock will be different from what they were prior to the faulting process.
Skorstad, Arne +4 more
openaire +1 more source

