Results 61 to 70 of about 21,529 (302)

3D Anodic Alumina Nanoarchitectures: A Decade of Progress from Foundational Science to Functional Metamaterials

open access: yesAdvanced Materials, EarlyView.
Ordered three‐dimensional anodic aluminum oxide (3D‐AAO) nanoarchitectures with longitudinal and transverse pores enable architecture‐driven metamaterials. The review maps fabrication advances, including hybrid pulse anodization, and shows how 3D‐AAO templates tailor properties across magnetism, energy, catalysis, and sensing.
Marisol Martín‐González
wiley   +1 more source

Meteorological Prediction Implemented on Field-Programmable Gate Array

open access: yes, 2013
In this work, a temperature predictor has been designed. The prediction is made by a multilayer perceptron neural network. Initially, the floating-point algorithm was evaluated.
Travieso, Carlos M.   +3 more
core   +1 more source

Neuromorphic Electronics for Intelligence Everywhere: Emerging Devices, Flexible Platforms, and Scalable System Architectures

open access: yesAdvanced Materials, EarlyView.
The perspective presents an integrated view of neuromorphic technologies, from device physics to real‐time applicability, while highlighting the necessity of full‐stack co‐optimization. By outlining practical hardware‐level strategies to exploit device behavior and mitigate non‐idealities, it shows pathways for building efficient, scalable, and ...
Kapil Bhardwaj   +8 more
wiley   +1 more source

A field programmable gate array-based crytographic system-on-chip

open access: yes, 2007
Information security is concerned with confidentiality, data integrity, nonrepudiation and authentication. It is the process of protecting data from unauthorized access, modification, or disruption in computer security and information assurance ...
M. Thamrin, Norashikin
core  

Path‐Decoupled Cation‐Eutaxy III–V van der Waals Memristive Semiconductors for Mitigating the Neuromorphic Accuracy‐Energy Trade‐off

open access: yesAdvanced Materials, EarlyView.
Path‐decoupled III–V van der Waals memtransistors spatially separate ionic and electronic transport to overcome the conventional trade‐off between accuracy and energy in neuromorphic hardware. Mobile K+ ions in the vdW gaps set a wide conductance window, Gmax/Gmin, while gate‐tunable hole conduction lowers programming energy, enabling reliable ...
Jihong Bae   +13 more
wiley   +1 more source

SOTB Implementation of a Field Programmable Gate Array with Fine-Grained Vt Programmability

open access: yesJournal of Low Power Electronics and Applications, 2014
Field programmable gate arrays (FPGAs) are one of the most widespread reconfigurable devices in which various functions can be implemented by storing circuit connection information and logic values into configuration memories.
Masakazu Hioki   +7 more
doaj   +1 more source

An RSFQ superconductive programmable gate array

open access: yes, 2007
Field-Programmable Gate Arrays (FPGAs) allow circuit reconfiguration in the field, which adds to the flexibility of electronic systems. Applied to superconductive electronics, reprogrammability allows system functionality to be changed without ...
Fourie C.J., Van Heerden H.
core   +1 more source

Switchable Magnonic Crystals Based on Spin Crossover/CrSBr Heterostructures

open access: yesAdvanced Materials, EarlyView.
Multiscale modeling is employed to investigate the functionality of a light‐controlled, tunable magnonic crystal based on spin‐crossover Fe‐pz molecules integrated with a monolayer of CrSBr. Ab initio simulations confirm that the molecules remain functional on the CrSBr surface, while a semiclassical elastic model demonstrates that light‐induced ...
Andrei Shumilin   +4 more
wiley   +1 more source

An FPGA-Based Hardware Accelerator for CNNs Using On-Chip Memories Only: Design and Benchmarking with Intel Movidius Neural Compute Stick

open access: yesInternational Journal of Reconfigurable Computing, 2019
During the last years, convolutional neural networks have been used for different applications, thanks to their potentiality to carry out tasks by using a reduced number of parameters when compared with other deep learning approaches.
Gianmarco Dinelli   +4 more
doaj   +1 more source

Built-In Self-Test Configurations for Field Programmable Gate Array Cores in Systems on Chip [PDF]

open access: yes, 2004
Built-In Self-Test configurations for the logic and routing resources present in the Field Programmable Gate Array core of a System-on-Chip is presented in this Thesis. These configurations completely test the Programmable Logic Blocks and Programmable
Harris, Jonathan
core  

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