Results 171 to 180 of about 47,684 (233)

Enhanced FPGA-based smart power grid simulation using Heun and Piecewise analytic method. [PDF]

Sci Rep
Gul U, Raza Ur Rehman HM, Gul MJ, Mezquita GM, Barrera AEP, Ashraf I.   +5 more
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Application and Comparison of FPGA-Based Carry Chain TDC and DDMTD Schemes in High-Precision Time Synchronization. [PDF]

Sensors (Basel)
Huang Y, Yu J, Xia W, Guo Q, Huang L.
europepmc   +1 more source

Overcoming quadratic hardware scaling for a fully connected digital oscillatory neural network. [PDF]

Front Neurosci
Haverkort BF, Todri-Sanial A.
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HUMaN: Handheld Ultrasound System with Magnetic Needle Navigation. [PDF]

Ultrasonography
Kye S, Cho M, Kim M, Berrocal M, Vera J, Song TK, Bae S.   +6 more
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Inter-Channel Error Calibration Method for Real-Time DBF-SAR System Based on FPGA. [PDF]

Sensors (Basel)
Meng Y, Qiu J, Wang P, Liu Y, Yang Z, Wei Y, Cheng X, Feng Y.   +7 more
europepmc   +1 more source

Entanglement-inspired frequency-agile rangefinding. [PDF]

Nat Commun
Nie W, Zhang P, McMillan A, Clark AS, Rarity JG.   +4 more
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The High-Energy Ion Telescope (HIT) for the Interstellar Mapping And Acceleration Probe (IMAP) Mission. [PDF]

Space Sci Rev
Christian ER, Mitchell JG, Bruno A, Albaijes D, Bailey Newman S, Boggs RC, Choi MK, Cohen CMS, Cook WR, Darwish YS, Davis AJ, de Nolfo GA, Dumonthier JJ, Garnett RD, Gkioulidou M, Gregory KJ, Guzman Garcia D, Haas JP, Hollenhorst C, Jeunon M, Kaiser MA, Kanekal SG, Kecman B, Leske RA, Letzer JD, Liceaga Indart I, McComas DJ, McNeel B, Muro GD, Nolan JT, Ogindo M, Petrowich P, Reaves WJ, Rosnack TP, Saghafi N, Salerno CL, Schwadron NA, Silber MA, Smith ES, Smith MT, Suárez G, Tatoli T, Tiu CP, Wiedenbeck ME, Windhausen MH, Xu Z.   +45 more
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Clock Gating Implementation on commercial Field Programmable Gate Array (FPGA)

2018 4th International Conference on Electrical, Electronics and System Engineering (ICEESE), 2018
This paper discusses the application and implementation of clock gating technique to RISC32 (a customizable processor on Field Programmable Gate Array (FPGA)) for reduction of dynamic power consumption on clock tree. The FPGA used is Artix-7 (xc7a100tcsg324-1) from Xilinx with 28nm technology. The power consumption of clock tree is reduced by 24% after
Wai-Kong Lee, Kai-Ming Mok
exaly   +2 more sources