Results 101 to 110 of about 47,559 (229)
Symbol‐Level GRAND‐Assisted Detection for Polar‐Coded Spatial Modulation in MIMO Systems
International Journal of Communication Systems, Volume 39, Issue 7, 10 May 2026.This research presents an integrated polar‐coded spatial modulation (PCSM) transceiver scheme for MIMO transmission over Rayleigh fading channels. The proposed architecture employs linear spatial signal processing for antenna and symbol estimation, followed by symbol‐level guessing random additive noise decoding (symbol‐level GRAND)–assisted detection ...
Abhilasha Gautam +2 more
wiley +1 more source
NEPP Independent Single Event Upset Testing of the Microsemi RTG4: Preliminary Data [PDF]
We present an independent investigation of heavy-ion single event effect data for the Microsemi RTG4 field programmable gate array (FPGA)
Berg, Melanie +2 more
core +1 more source
Experimental High‐Throughput Electrochemistry
ChemElectroChem, Volume 13, Issue 9, 5 May 2026.This review highlights experimental high‐throughput electrochemistry as a powerful approach to accelerate electrochemical research. Key technologies such as automated platforms, microelectrode arrays, and machine learning‐based optimization are discussed, with a focus on applications in electrocatalysis, battery research, and electrosynthesis ...
Jens Noack
wiley +1 more source
Enhanced Efficiency 3D Convolution Based on Optimal FPGA Accelerator
IEEE Access, 2017 This paper presents an enhanced efficiency 3-D convolution operator based on optimal field programmable gate array (FPGA) accelerator platform. The proposed system takes advantages of the intermediate data delay lines, implemented in an FPGA, to avoid ...
Hai Wang +3 more
doaj +1 more source
Actel Parts Usage in GSFC Projects [PDF]
, 2006 The purpose of this paper is to provide an overview of the Actel field programmable gate array (FPGA) issues and investigations to date, provide information to GSFC parts engineers on the risks associated with the use of these parts in flight, provide ...
Sahu, Kusum
core +1 more source
Computer Applications in Engineering Education, Volume 34, Issue 3, May 2026.ABSTRACT Massive Open Online Courses (MOOCs) have established a new paradigm in education, enabling asynchronous, remote learning. Although MOOCs offer diverse educational content to students, comprehensive and realistic education requires hands‐on training.
Manuel J. Gomez +6 more
wiley +1 more source
Optimization and Benchmarking of Lightweight Neural Networks for Efficient Embedded AI Deployment
Engineering Reports, Volume 8, Issue 5, May 2026.A hardware‐aware optimization and benchmarking framework for lightweight neural networks is presented for deployment on heterogeneous embedded platforms including CPU, GPU, TPU, and MCU architectures. Model compression techniques such as quantization, pruning, knowledge distillation, and mixed‐precision computation reduce inference latency, memory ...
Vidapankal Mohammad Fridous +4 more
wiley +1 more source
FPGA Boot Loader and Scrubber [PDF]
A computer program loads configuration code into a Xilinx field-programmable gate array (FPGA), reads back and verifies that code, reloads the code if an error is detected, and monitors the performance of the FPGA for errors in the presence of radiation.
Jones, Bailey, Wade, Randall S.
core +1 more source
Reprogrammable All‐Photonic Molecular Logic With Ln3+ Luminescent Hybrids in Solid State
Laser &Photonics Reviews, Volume 20, Issue 9, 6 May 2026.Mario P. de‐Saralegui et al. report an Eu3⁺/Tb3⁺‐doped organic–inorganic hybrid material that enables multiple reprogrammable logic operations using only physical stimuli. Additionally, this solid‐state, all‐photonic platform represents the first example in the literature performing reversible Feynman logic operations, marking a major step toward ...
Mario P. de‐Saralegui +4 more
wiley +1 more source
Design and Implementation of JPEG 2000 Image Compression using FPGA
Journal of Engineering and Sustainable Development, 2006 This paper investigates the use of a Field Programmable Gate Array (FPGA Xilinx Virtex-II) to perform hardware implementation for low speed part of JPEG2000 to achieve a real time JPEG2000 system.
Munther N. B. Al-Tikriti +2 more
doaj