Results 51 to 60 of about 649,732 (345)
Programmable quantum gate arrays [PDF]
, 1997 We show how to construct quantum gate arrays that can be programmed to perform different unitary operations on a data register, depending on the input to some program register. It is shown that a universal quantum gate array - a gate array which can be programmed to perform any unitary operation - exists only if one allows the gate array to operate in ...
arxiv +1 more source
Design of FPGA-Based LZ77 Compressor With Runtime Configurable Compression Ratio and Throughput
IEEE Access, 2019 Data compression reduces the cost of data storage and transmission by decreasing the data size. Previous studies have improved system performance by adaptively choosing the compression ratio (CR) and throughput required for the system by using a trade ...
Seungdo Choi +6 more
doaj +1 more source
Analysis and Comparison of FPGA-Based Histogram of Oriented Gradients Implementations
IEEE Access, 2020 One of the commonly-used feature extraction algorithms in computer vision is the histogram of oriented gradients. Extracting the features from an image using this algorithm requires a large amount of computations.
Sina Ghaffari +3 more
doaj +1 more source
Blinding HT: Hiding Hardware Trojan signals traced across multiple sequential levels
IET Circuits, Devices and Systems, 2022 Modern electronic systems usually use third‐party IP cores to build basic blocks. However, there may be Hardware Trojans (HTs) in IP cores, which will cause critical security problem.
Ying Zhang +4 more
doaj +1 more source
Tunable Tactile Synapses Enabled by Erasable Doping in Iongel‐Gated Nanotube Network Transistors
Advanced Functional Materials, EarlyView.Artificial tactile synaptic sensors are realized by an iongel‐gated single‐walled carbon nanotube (SWCNT) transistor with reversible doping characteristics. The device senses and memorizes tactile stimuli and exhibits gate bias‐dependent excitatory or inhibitory synaptic behavior.
Yan Huang +5 more
wiley +1 more source
IET Circuits Devices Syst., 2013 Number plate localisation is a very important stage in an automatic number plate recognition (ANPR) system and is computationally intensive. This study presents a low complexity with high-detection rate number plate localisation algorithm based on ...
X. Zhai, F. Bensaali, S. Ramalingam
semanticscholar +1 more source
A Simple Approach of Space-vector Pulse Width Modulation Realization Based on Field Programmable Gate Array [PDF]
, 2010 Employing a field programmable gate array to realize space-vector pulse width modulation is a solution to boost system performance. Although there is much literature in the application of three-phase space-vector pulse width modulation based on field ...
Jidin, Auzani +3 more
core +1 more source
The NAIL Accelerator Interface Layer for Low Latency FPGA Offload
IEEE AccessWe present the NAIL Accelerator Interface Layer, a framework for offloading accelerated computations to Field Programmable Gate Arrays served across the network.
Edward Grindley +8 more
doaj +1 more source
Area Optimisation for Field-Programmable Gate Arrays in SystemC Hardware Compilation
International Journal of Reconfigurable Computing, 2008 This paper discusses a pair of synthesis algorithms that optimise a SystemC design to minimise area when targeting FPGAs. Each can significantly improve the synthesis of a high-level language construct, thus allowing a designer to concentrate more on an ...
Johan Ditmar +2 more
doaj +1 more source
Gate‐Tunable Hole Transport in In‐Plane Ge Nanowires by V‐Groove Confined Selective Epitaxy
Advanced Functional Materials, EarlyView.Ge nanowires are promising for hole spin‐based quantum processors, requiring direct integration onto Si wafers. This work introduces V‐groove‐confined selective epitaxy for in‐plane nanowire growth on Si. Structural and low‐temperature transport measurements confirm their high crystalline quality, gate‐tunable hole densities, and mobility.
Santhanu Panikar Ramanandan +11 more
wiley +1 more source