Results 241 to 250 of about 12,597 (299)
Reliability of floating gate memories
, 2008 This chapter aims at giving an overview of the most important reliability issues affecting the floating gate memory technology which are the key elements whose evaluation is on the basis of each ECC strategy. Reliability issues will be discussed by considering the single cell first (intrinsic cell degradation) and then by introducing all the important ...
CHIMENTON, Andrea, M. Atti, OLIVO, Piero
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Double-Floating-Gate van der Waals Transistor for High-Precision Synaptic Operations
ACS Nano, 2023 Two-dimensional materials and their heterostructures have thus far been identified as leading candidates for nanoelectronics owing to the near-atom thickness, superior electrostatic control, and adjustable device architecture.
Hoyeon Cho, Donghyun Lee, Der-Yuh Lin
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Error Instability in Floating Gate Flash Memories Exposed to TID
IEEE Transactions on Nuclear Science, 2009 We discuss new experimental results on the post-radiation annealing of Floating Gate errors in Flash memories with both NAND and NOR architecture. We investigate the dependence of annealing on the program level, linking the reduction in the number of ...
Marta Bagatin +2 more
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2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512), 2004
The precision of digital-to-analog converters (DAC) is always limited by element mismatching. These elements can be transistors, resistors, capacitors, etc. Techniques used to improve resolution often involve the sacrifice of die area. In this paper we present a design for a DAC using floating-gate MOS transistors.
Guillermo J. Serrano, Paul E. Hasler
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The precision of digital-to-analog converters (DAC) is always limited by element mismatching. These elements can be transistors, resistors, capacitors, etc. Techniques used to improve resolution often involve the sacrifice of die area. In this paper we present a design for a DAC using floating-gate MOS transistors.
Guillermo J. Serrano, Paul E. Hasler
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Indirect Programming of Floating-Gate Transistors
IEEE Transactions on Circuits and Systems I: Regular Papers, 2005Floating-gate (FG) transistors are useful for precisely programming a large array of current sources. Present FG programming techniques require disconnection of the transistor from the rest of its circuit while it is being programmed. We present a new method of programming FG transistors that does not require this disconnection.
David W. Graham +4 more
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A buck converter with float gate width and float gate voltage driver
2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), 2016A float gate width and float gate voltage driver is proposed in this paper, which is applied in double N-type power MOSFETs buck converter with large load driving capacity to improve the efficiency. The relationships between the total power dissipation with the gate width and gate voltage are analyzed firstly.
null Ping Luo +4 more
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Proposal for a Bidirectional Gate Using Pseudo Floating-Gate
4th IEEE International Symposium on Electronic Design, Test and Applications (delta 2008), 2008In this paper we propose a bidirectional logic gate. The advantages of this gate lie in the use of floating-gate, thus making the gate operate on voltage variations across capacitors. We show that by applying the reference signals as clock or control signals we are able to define the signal direction.
Omid Mirmotahari, Yngvar Berg
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Analysis of the floating gate defect in CMOS
Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 2002The floating gate transistor is modeled using the coupling capacitances in the floating gate and the charge in the transistor gate. The location of the open in the open track influences the value of the poly-bulk and metal-poly capacitances who determines the degree of conduction of the defective transistor. The induced voltage in the floating gate and
Víctor H. Champac +2 more
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Research on floating-gate ISFET biosensor
Proceedings of 2011 International Conference on Electronic & Mechanical Engineering and Information Technology, 2011By the analysis of the sensing mechanism of ISFET, A HSPICE behavioral model of a floating-gate ISFET is built based on the site-binding model. Its static input-output characteristics are simulated and the relationship between the membrane resistance, membrane capacitance, interconnection line parasitic capacitance and the dynamic characteristics of ...
Mingfei Wei +3 more
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Floating Gate Perimeter Gated Single Photon Avalanche Diodes
2020 IEEE 15th International Conference on Nano/Micro Engineered and Molecular System (NEMS), 2020This paper explores the effect of floating gate structures on the electric field distribution of perimeter gate single photon avalanche diodes using TCAD Sentaurus simulations. Physical models used for the simulation have been discussed extensively to expedite reproduction of simulation results in other simulation platforms.
Mohammad Aminul Haque, Nicole McFarlane
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