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Calibration and matching of floating gate devices
2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353), 2002We measure the matching characteristics of floating gate MOSFET devices. Arrays of ten FG PFET devices were fabricated on two different runs of the same process. Matching characteristics were measured: (1) direct from the foundry, (2) after Fowler-Nordheim tunneling, (3) after self-limiting PFET hot-electron injection, and (4) after UV exposure.
Wesley P. Millard +2 more
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Programmable Floating-Gate CMOS Resistors
2005 IEEE International Symposium on Circuits and Systems, 2005In this paper, we propose implementations of highly linear floating-gate CMOS resistors that can be fully integrated in CMOS technology. Also, we analyze the second order effects of a single transistor operating in the linear operation regime and apply a linearization technique to suppress these nonlinearities.
Erhan Ozalevli, Paul E. Hasler
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A dual-gate floating-gate FET device
1981 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, 1981An experimental floating-gate FET with two capacitively-coupled control gates for nonvolatile and electrically alterable application will be discussed. An enhanced conduction insulator under one control gate serves to charge/discharge the floating gate.
H. Kotecha, null Chung Lam
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2011 IEEE Global Telecommunications Conference - GLOBECOM 2011, 2011
Flash memory comprises of grid of cells arranged in a rectangular lattice. A cell is a floating gate and the information is stored as charge in these floating gates. A multi-level-cell (MLC) can store more than one bit per cell. An ideal programming of a cell consists of injecting just the correct amount of charge in the cell by hot-electron injection.
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Flash memory comprises of grid of cells arranged in a rectangular lattice. A cell is a floating gate and the information is stored as charge in these floating gates. A multi-level-cell (MLC) can store more than one bit per cell. An ideal programming of a cell consists of injecting just the correct amount of charge in the cell by hot-electron injection.
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Reversible floating-gate memory
Journal of Applied Physics, 1973Reversible memory behavior is reported for an insulated gate structure, in which charge is stored on a polysilicon gate. This gate is floating between layers of silicon dioxide (SiO2) and silicon nitride (Si3N4). The floating gate is charged negatively by hot carrier injection through the SiO2, from an avalanche plasma in the underlying silicon.
H. C. Card, A. G. Worrall
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Floating-gate techniques for assessing mismatch
2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353), 2002I discuss the importance of capacitor matching in the context of using charge stored on floating-gate MOS (FGMOS) transistors to compensate for transistor mismatch in analog circuits. I describe a simple technique that only involves static measurements for assessing the relative mismatch between capacitors.
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An autozeroing floating-gate amplifier
IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 2001We have developed a bandpass floating-gate amplifier that uses tunneling and pFET hot-electron injection to set its dc operating point adaptively. Because the hot-electron injection is an inherent part of the pFET's behavior, we obtain this adaptation with no additional circuitry.
P. Hasler, B.A. Minch, C. Diorio
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A floating-gate vector-quantizer
The 2002 45th Midwest Symposium on Circuits and Systems, 2002. MWSCAS-2002., 2003We present a floating-gate based system for computing vector quantization (VQ), which is typically used for data compression and classification of signals to symbols. We present an architecture and resulting circuits which will enable direct programming/storage of weight vectors, as well as methods for adaptive VQ.
P. Hasler +5 more
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Floating gate memories reliability
Quality and Reliability Engineering International, 1992AbstractBesides conventional IC failure mechanisms, the floating gate (FG) device reliability is affected by data retention, characteristic of non‐volatile memories, and endurance, typical of electrically erasable arrays.The subjects of this work are EPROM and flash EEPROM, the leading and most promising devices among the FG non‐volatile memories.The ...
G. Crisenza +3 more
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IEEE International Workshop on Biomedical Circuits and Systems, 2004., 2005
This paper presents a flexible biasing-method for floating gate circuits. The biasing technique preserves the floating gate nature of the well known floating gate modules at the same time as it provides an effective way to adjust the gate bias level continuously.
T. Halvorsrod, O. Naess, T. Lande
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This paper presents a flexible biasing-method for floating gate circuits. The biasing technique preserves the floating gate nature of the well known floating gate modules at the same time as it provides an effective way to adjust the gate bias level continuously.
T. Halvorsrod, O. Naess, T. Lande
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