Results 231 to 240 of about 260,838 (285)
Some of the next articles are maybe not open access.
Analysis of floating point operations in microcontrollers
2011 Proceedings of IEEE Southeastcon, 2011The purpose of this paper is to identify the advantages of including a floating point hardware / a mathematical co-processor in microcontrollers used for critical floating point operations. Three different microcontrollers are considered: Renesas M16C/62P (CISC without FPU), ATMEGA1280 (RISC without MCU) and Renesas RX62N (CISC with FPU).
Aswin Ramakrishnan, James M. Conrad
exaly +2 more sources
Accelerating Microblaze Floating Point Operations
2007 International Conference on Field Programmable Logic and Applications, 2007The MicroBlaze processor serves in many FPGA designs as the central 32 bit CPU with access to the global off chip memory and peripherals. MicroBlaze provides FSL links for up to 8 coprocessors. We present two MicroBlaze designs. The first design works with 8 PicoBlaze-based accelerators for pipelined, single-precision floating point vector-oriented ...
Jiri Kadlec +2 more
openaire +1 more source
Semantics for exact floating point operations
[1991] Proceedings 10th IEEE Symposium on Computer Arithmetic, 2002Semantics are given for the four elementary arithmetic operations and the square root, to characterize what are termed exact floating point operations. The operands of the arithmetic operations and the argument of the square root are all floating point numbers in one format.
Bohlender, Gerd +3 more
openaire +1 more source
Accurate floating-point operation using controlled floating-point precision
Proceedings of 2011 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing, 2011Rounding and accumulation of errors when using floating point numbers are important factors in computer arithmetic. Many applications suffer from these problems. The underlying machine architecture and representation of floating point numbers play the major role in the level and value of errors in this type of calculations.
Ahmad M. Zaki +3 more
openaire +1 more source
Formalization and implementation of floating-point matrix operations
Computing, 1976The paper shows that floating-point matrix operations can be implemented in a way which leads to reasonable mathematical structures as well as to sensible compatibility properties between these structures and the structure of the real matrices. It turns out, for instance, that all the rules of the minus-operator for real matrices can be saved and that ...
Ulrich W. Kulisch, Gerd Bohlender
openaire +1 more source
An accelerator for double precision floating point operations
Eleventh Euromicro Conference on Parallel, Distributed and Network-Based Processing, 2003. Proceedings., 2003We describe DPFPA (double precision floating point accelerator) an FPGA based coprocessor interfaced to the CPU through the PCI bus; it is conceived to accelerate the evaluation of double precision floating point operations. This coprocessor is based on two double precision floating point units: a pipelined adder and a pipelined multiplier. The work is
Giovanni Danese +4 more
openaire +1 more source
Improving the ratio of memory operations to floating-point operations in loops
ACM Transactions on Programming Languages and Systems, 1994Over the past decade, microprocessor design strategies have focused on increasing the computational power on a single chip. Because computations often require more data from cache per floating-point operation than a machine can deliver and because operations are pipelined, idle computational cycles are common when scientific applications are executed ...
Steve Carr 0001, Ken Kennedy
openaire +1 more source
VHDL Floating Point Operations
1995In this paper, we present a set of portable floating point VHDL functions. These functions provide the VHDL programmer with absolute portability and very precise control over floating point operations. A single VHDL type is used to represent single, double, and extended precision floating point numbers.
George S. Powley, Joanne E. DeGroat
openaire +1 more source
Parameterisable floating-point operations on FPGA
Conference Record of the Thirty-Sixth Asilomar Conference on Signals, Systems and Computers, 2002., 2003The paper presents a group of IEEE 754-style floating-point units targeted at Xilinx VirtexII FPGA. Special features of the technology are taken advantage of to produce optimised components. Pipelined designs are given that show the latency of /spl sim/100 MHz single-precision components.
B. Lee, N. Burgess
openaire +1 more source

