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Formal Verification in Railways
1999The motive for adopting a formal method is an improved development process with resource savings, a reduced number of errors, and reduced time-to-market. That formal methods potentially can give these benefits is not very controversial since formal methods consider software construction just like construction in any other traditional engineering ...
Arne Borälv, Gunnar Stålmarck
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Formal verification of Ada programs
IEEE Transactions on Software Engineering, 1990The Penelope verification editor and its formal basis are described. Penelope is a prototype system for the interactive development and verification of programs that are written in a rich subset of sequential Ada. Because it generates verification conditions incrementally, Penelope can be used to develop a program and its correctness proof in concert ...
David Guaspari +2 more
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Formal Verification and Debugging
2010This chapter introduces approaches for formal verification and debugging and therewith completes the proposed approaches towards a design flow for reversible logic. Verification is an essential step that ensures whether obtained designs in fact realize the desired functionality or not.
Rolf Drechsler, Robert Wille
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Formal modeling and verification of microprocessors
IEEE Transactions on Computers, 1995Summary: Formal verification has long been promised as a means of reducing the amount of testing required to ensure correct VLSI devices. Verification requires at least two mathematical models: one that describes the structure of a computer system and another that models its intended behavior. These models are called specifications.
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ACM SIGDA Newsletter, 2005
Formal verification is the use of mathematical techniques to ensure that a design conforms to some precisely expressed notion of functional correctness. Concretely, assume that you have (1) a model of a design, (2) some description of the environment that the design is supposed to operate in, and (3) some properties that the design is intended to ...
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Formal verification is the use of mathematical techniques to ensure that a design conforms to some precisely expressed notion of functional correctness. Concretely, assume that you have (1) a model of a design, (2) some description of the environment that the design is supposed to operate in, and (3) some properties that the design is intended to ...
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2005
These lecture notes present a set of techniques for the verification of reactive systems. We concentrate on the case of infinite-states systems and the application of abstraction methods for their verification.
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These lecture notes present a set of techniques for the verification of reactive systems. We concentrate on the case of infinite-states systems and the application of abstraction methods for their verification.
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Design Automation for Field-coupled Nanotechnologies, 2021
Marcel Walter +3 more
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Marcel Walter +3 more
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Formal verification of parallel programs
Communications of the ACM, 1976Two formal models for parallel computation are presented: an abstract conceptual model and a parallel-program model. The former model does not distinguish between control and data states. The latter model includes the capability for the representation of an infinite set of control states by allowing there to be arbitrarily many instruction pointers (or
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Formal verification of an optimizing compiler
2007 5th IEEE/ACM International Conference on Formal Methods and Models for Codesign (MEMOCODE 2007), 2007Programmers naturally expect that compilers and other code generation tools produce executable code that behaves as prescribed by source programs. However, compilers are complex programs that perform many subtle transformations. Bugs in compilers do happen and can lead to silently producing incorrect executable code from a correct source program.
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Towards formal verification of IoT protocols: A Review
Comput. Networks, 2020Katharina Hofer-Schmitz +1 more
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