Results 41 to 50 of about 3,157,454 (357)
Formal Verification of Three-Valued Digital Waveforms
Моделирование и анализ информационных систем, 2019 We investigate a formal verification problem (mathematically rigorous correctness checking) for digital waveforms used in practical development of digital microelectronic devices (digital circuits) at early design stages.
Nina Yu. Kutsak, Vladislav V. Podymov
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Formal verification of monad transformers [PDF]
ACM SIGPLAN Notices, 2012 We present techniques for reasoning about constructor classes that (like the monad class) fix polymorphic operations and assert polymorphic axioms. We do not require a logic with first-class type constructors, first-class polymorphism, or type quantification; instead, we rely on a domain-theoretic model of the type system in a universal domain to ...
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Formal verification of a deadlock detection algorithm [PDF]
Electronic Proceedings in Theoretical Computer Science, 2011 Deadlock detection is a challenging issue in the analysis and design of on-chip networks. We have designed an algorithm to detect deadlocks automatically in on-chip networks with wormhole switching.
Freek Verbeek, Julien Schmaltz
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Formal specification and verification [PDF]
, 2019 Beyond his seminal contributions to the theory and the design of concurrent and distributed algorithms, Leslie Lamport has throughout his career worked on methods and formalisms for rigorously establishing the correctness of algorithms.
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Verifications of a formal technique for viscoelastodynamics [PDF]
Bulletin of the Australian Mathematical Society, 1974 Presented in this paper are justifications for the formal Karal-Keller technique as it applies to propagation, reflection, and transmission of one-dimensional impact waves in nonhomogeneous viscoelastic solids.
T. Bryant Moodie, D. W. Barclay
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Formal Verification of Code Conversion: A Comprehensive Survey
TechnologiesCode conversion, encompassing translation, optimization, and generation, is becoming increasingly critical in information systems and the software industry.
Amira T. Mahmoud +7 more
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Simulator Semantics for System Level Formal Verification [PDF]
Electronic Proceedings in Theoretical Computer Science, 2015 Many simulation based Bounded Model Checking approaches to System Level Formal Verification (SLFV) have been devised. Typically such approaches exploit the capability of simulators to save computation time by saving and restoring the state of the system ...
Toni Mancini +4 more
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Disruption of SETD3‐mediated histidine‐73 methylation by the BWCFF‐associated β‐actin G74S mutation
FEBS Letters, EarlyView.The β‐actin G74S mutation causes altered interaction of actin with SETD3, reducing histidine‐73 methylation efficiency and forming two distinct actin variants. The variable ratio of these variants across cell types and developmental stages contributes to tissue‐specific phenotypical changes. This imbalance may impair actin dynamics and mechanosensitive
Anja Marquardt +8 more
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Formal Verification of Real-Time System Requirements [PDF]
Computer Science, 2000 The methodology of system requirements verification presented in this paper is a proposition of a practical procedure for reducing some negatives of the specification of requirements.
Marcin Szpyrka
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Integrating UML With Service Refinement for Requirements Modeling and Analysis
IEEE Access, 2019 The Unified Modeling Language (UML) is the de facto standard for requirements modeling and analysis in the software industry. However, it lacks the ability of formal analysis and verification.
Yilong Yang +3 more
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