Results 161 to 170 of about 196,878 (200)
Scheduling algorithms for automated synthesis of pipelined designs on FPGAs for applications described in MATLAB [PDF]
Malay Haldar+3 more
openalex +1 more source
Abstract Purpose We introduce the next generation of “MagicPlate” 2D monolithic pixelated semiconductor detectors – MagicPlate‐976 (MP976). It features a larger array area, higher spatial resolution, and does not require external triggering. We perform a comprehensive characterization for small‐field steep‐dose‐gradient dosimetry applications in ...
Ilia Filipev+13 more
wiley +1 more source
Challenging Portability Paradigms: FPGA Acceleration Using SYCL and OpenCL [PDF]
As the interest in FPGA-based accelerators for HPC applications increases, new challenges also arise, especially concerning different programming and portability issues. This paper aims to provide a snapshot of the current state of the FPGA tooling and its problems. To do so, we evaluate the performance portability of two frameworks for developing FPGA
arxiv
Tolerating operational faults in cluster-based FPGAs [PDF]
Vijay Lakamraju, Russell Tessier
openalex +1 more source
Abstract Background FLASH has been shown to spare normal tissue toxicity while maintaining tumor control. However, existing irradiation platforms and dosimetry are not compatible. Consequently, an abundance of FLASH delivery devices and new dosimetry across all modalities has been created.
Justin DeFrancisco, Siyong Kim
wiley +1 more source
Hardware-software cosynthesis for run-time incrementally reconfigurable FPGAs [PDF]
Byungil Jeong+3 more
openalex +1 more source
This review focuses on optical, electric, and magnetic nanotweezers for manipulating single micro/nanoparticles as miniaturized biomedical tools. Representative historical and contemporary examples illustrate mechanisms, setups, performance, and applications.
Kelly Shih+4 more
wiley +1 more source
Structural gate decomposition for depth-optimal technology mapping in LUT-based FPGA designs [PDF]
Jason Cong, Yean-Yow Hwang
openalex +1 more source
An Efficient Multi‐Core DSP Power Management Controller
This work proposes a power management controller for multi‐core DSP architectures, specifically designed for FT‐xDSP. The primary contributions include a clamp request control unit to ensure system stability during asynchronous resets, and a configurable state transition counter that optimizes clock transitions.
Jian Huang+4 more
wiley +1 more source
Automatic generation of FPGA routing architectures from high-level descriptions [PDF]
Vaughn Betz, Jonathan Rose
openalex +1 more source