Results 11 to 20 of about 245,820 (308)
Application Acceleration on FPGAs with OmpSs@FPGA [PDF]
2018 International Conference on Field-Programmable Technology (FPT), 2018 OmpSs@FPGA is the flavor of OmpSs that allows offloading application functionality to FPGAs. Similarly to OpenMP, it is based on compiler directives. While the OpenMP specification also includes support for heterogeneous execution, we use OmpSs and OmpSs@FPGA as prototype implementation to develop new ideas for OpenMP. OmpSs@FPGA implements the tasking
Bosch, Jaume +9 more
openaire +2 more sources
Constructing cluster of simple FPGA boards for cryptologic computations [PDF]
, 2012 In this paper, we propose an FPGA cluster infrastructure, which can be utilized in implementing cryptanalytic attacks and accelerating cryptographic operations.
Doroz, Yarkin +3 more
core +1 more source
Dynamic reconfiguration technologies based on FPGA in software defined radio system [PDF]
, 2011 Partial Reconfiguration (PR) is a method for Field Programmable Gate Array (FPGA) designs which allows multiple applications to time-share a portion of an FPGA while the rest of the device continues to operate unaffected.
Ke He +3 more
core +2 more sources
FMCW rail-mounted SAR: Porting spotlight SAR imaging from MATLAB to FPGA [PDF]
, 2014 In this work, a low-cost laptop-based radar platform derived from the MIT open courseware has been implemented. It can perform ranging, Doppler measurement and SAR imaging using MATLAB as the processor.
Gray, D., Le Kernec, J., Melnikov, A.
core +1 more source
Effects of FPGA architecture on FPGA routing [PDF]
Proceedings of the 32nd ACM/IEEE conference on Design automation conference - DAC '95, 1995 Although many traditional Mask Programmed Gate Array (MPGA) algorithms can be applied to FPGA routing, FPGA architectures impose critical constraints and provide alternative views of the routing problem that allow innovative new algorithms to be applied.
openaire +1 more source
SVITE: A Spike-Based VITE Neuro-Inspired Robot Controller [PDF]
, 2013 This paper presents an implementation of a neuro-inspired algorithm called VITE (Vector Integration To End Point) in FPGA in the spikes domain. VITE aims to generate a non-planned trajectory for reaching tasks in robots. The algorithm has been adapted
Domínguez Morales, Manuel Jesús +4 more
core +1 more source
Predictive control using an FPGA with application to aircraft control [PDF]
, 2013 Alternative and more efficient computational methods can extend the applicability of MPC to systems with tight real-time requirements. This paper presents a “system-on-a-chip” MPC system, implemented on a field programmable gate array (FPGA), consisting ...
Constantinides, GA +5 more
core +1 more source
Real time implementation of separating overlapped algorithm for dual array ADS-B signal
Dianzi Jishu Yingyong, 2020 In order to solve the problem of signal overlapping when communicating in ADS-B system, combined with the working characteristics of FPGA and the requirements of real-time system, the ADS-B overlapping detection algorithm and separating overlapped ...
Hu Tieqiao, Han Bin
doaj +1 more source
Practical realization of space-time filtering of satellite navigation signals in real time
Физика волновых процессов и радиотехнические системы, 2023 Background. The problem of satellite navigation signals’ jamming-protected receivers design is quite relevant due to the high vulnerability of such signals to the influence of interferences whose sources number is constantly increasing. Aim.
Yevgeniy I. Glushankov +1 more
doaj +1 more source
Hardware acceleration of number theoretic transform for zk‐SNARK
Engineering Reports, EarlyView., 2023 An FPGA‐based hardware accelerator with a multi‐level pipeline is designed to support the large‐bitwidth and large‐scale NTT tasks in zk‐SNARK. It can be flexibly scaled to different scales of FPGAs and has been equipped in the heterogeneous acceleration system with the help of HLS and OpenCL.
Haixu Zhao +6 more
wiley +1 more source