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FPGA IMPLEMENTATIONS OF NEURAL NETWORKS
Universum:Technical sciences, 2023 This introductory chapter reviews the basics of artificial-neural-network theory, discusses various aspects of the hardware implementation of neural networks (in both ASIC and FPGA technologies, with a focus on special features of artificial neural ...
A. Omondi, Jagath Rajapakse
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FPGA-Based Near-Memory Acceleration of Modern Data-Intensive Applications [PDF]
IEEE Micro, 2021 Modern data-intensive applications demand high computational capabilities with strict power constraints. Unfortunately, such applications suffer from a significant waste of both execution cycles and energy in current computing systems due to the costly ...
Gagandeep Singh +6 more
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Start Acceleration of the Space GPS Receiver [PDF]
International Journal of Electronics and Telecommunications, 2020 The cold start of the space GPS receiver, i.e. the start without any information about the receiver position, satellite constellation, and time, is complicated by a large Doppler shift of a navigation signal caused by the satellite movement on the Earth ...
Pavel Kovář
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Sampler – Open-Source Data Acquisition Module for Quantum Physics [PDF]
International Journal of Electronics and Telecommunications, 2022 The Sinara hardware platform is a modular, opensource measurement and control system dedicated to quantum applications that require hard real-time performance.
Grzegorz Kasprowicz +8 more
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OmpSs@FPGA framework for high performance FPGA computing [PDF]
IEEE Transactions on Computers, 2021 This paper presents the new features of the OmpSs@FPGA framework. OmpSs is a data-flow programming model that supports task nesting and dependencies to target asynchronous parallelism and heterogeneity. OmpSs@FPGA is the extension of the programming model addressed specifically to FPGAs.
Haro Ruiz, Juan Miguel de +8 more
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Fixed-latency System for High-speed Serial Transmission Between FPGA Devices with Forward Error Correction [PDF]
International Journal of Electronics and Telecommunications, 2020 This paper presents the design of a compact protocol for fixed-latency, high-speed, reliable, serial transmission between simple field-programmable gate arrays (FPGA) devices.
Michał Kruszewski +1 more
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Architecture design of re-configurable convolutional neural network on software definition
网络与信息安全学报, 2021 In order to meet the flexibility and efficiency requirement in convolutional neural network (CNN), an architecture of re-configurable CNN based on software definition was proposed.
LI Peijie, ZHANG Li +1 more
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FPGA: Fast Patch-Free Global Learning Framework for Fully End-to-End Hyperspectral Image Classification [PDF]
IEEE Transactions on Geoscience and Remote Sensing, 2020 Deep learning techniques have provided significant improvements in hyperspectral image (HSI) classification. The current deep learning-based HSI classifiers follow a patch-based learning framework by dividing the image into overlapping patches.
Zhuo Zheng +3 more
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NPE: An FPGA-based Overlay Processor for Natural Language Processing [PDF]
Symposium on Field Programmable Gate Arrays, 2021 In recent years, transformer-based models have shown state-of-the-art results for Natural Language Processing (NLP). In particular, the introduction of the BERT language model brought with it breakthroughs in tasks such as question answering and natural ...
H. Khan +5 more
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High-Performance Accurate and Approximate Multipliers for FPGA-Based Hardware Accelerators
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2021 Multiplication is one of the widely used arithmetic operations in a variety of applications, such as image/video processing and machine learning. FPGA vendors provide high-performance multipliers in the form of DSP blocks.
Salim Ullah +3 more
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