Results 31 to 40 of about 86,072 (259)
Caffeinated FPGAs: FPGA framework For Convolutional Neural Networks [PDF]
2016 International Conference on Field-Programmable Technology (FPT), 2016 Convolutional Neural Networks (CNNs) have gained significant traction in the field of machine learning, particularly due to their high accuracy in visual recognition. Recent works have pushed the performance of GPU implementations of CNNs to significantly improve their classification and training times.
Roberto DiCecco +5 more
openaire +2 more sources
A novel edge computing approach to astronomical image data processing based on sCMOS camera using SoC [PDF]
International Journal of Electronics and TelecommunicationsThe ever-growing deluge of astronomical data challenges traditional server-based processing, hindering real-time analysis and scientific discovery. This paper proposes a novel approach: edge computing directly on an sCMOS camera using a System-on-Chip ...
Paweł Zienkiewicz +8 more
doaj +1 more source
A C++-embedded Domain-Specific Language for programming the MORA soft processor array [PDF]
, 2010 MORA is a novel platform for high-level FPGA programming of streaming vector and matrix operations, aimed at multimedia applications. It consists of soft array of pipelined low-complexity SIMD processors-in-memory (PIM).
Purohit, S. +7 more
core +1 more source
Connection Science, 2018 In human speech, the timing function is important for determining its duration, stress and rhythm; however, little attention has been paid to these issues when building a speech synthesis system. In the human brain, the cerebellum plays a key role in the
Vo Nhu Thanh, Hideyuki Sawada
doaj +1 more source
An area-efficient 2-D convolution implementation on FPGA for space applications [PDF]
, 2011 The 2-D Convolution is an algorithm widely used in image and video processing. Although its computation is simple, its implementation requires a high computational power and an intensive use of memory.
Stefano Di Carlo +11 more
core +1 more source
Hardware acceleration of number theoretic transform for zk‐SNARK
Engineering Reports, EarlyView., 2023 An FPGA‐based hardware accelerator with a multi‐level pipeline is designed to support the large‐bitwidth and large‐scale NTT tasks in zk‐SNARK. It can be flexibly scaled to different scales of FPGAs and has been equipped in the heterogeneous acceleration system with the help of HLS and OpenCL.
Haixu Zhao +6 more
wiley +1 more source
Practical realization of space-time filtering of satellite navigation signals in real time
Физика волновых процессов и радиотехнические системы, 2023 Background. The problem of satellite navigation signals’ jamming-protected receivers design is quite relevant due to the high vulnerability of such signals to the influence of interferences whose sources number is constantly increasing. Aim.
Yevgeniy I. Glushankov +1 more
doaj +1 more source
GRAph Parallel Actor Language: A Programming Language for Parallel Graph Algorithms [PDF]
, 2013 We introduce a domain-specific language, GRAph Parallel Actor Language, that enables parallel graph algorithms to be written in a natural, high-level form.
DeLorimier, Michael John
core +1 more source
Real time implementation of separating overlapped algorithm for dual array ADS-B signal
Dianzi Jishu Yingyong, 2020 In order to solve the problem of signal overlapping when communicating in ADS-B system, combined with the working characteristics of FPGA and the requirements of real-time system, the ADS-B overlapping detection algorithm and separating overlapped ...
Hu Tieqiao, Han Bin
doaj +1 more source
Hardware design of convolution calculation module based on systolic array
Dianzi Jishu Yingyong, 2020 Aiming at the long broadcast, much fan in/fan out data path problem brought by high parullelism in the process of the Field Programmable Gate Array(FPGA) to realize the convolution computation in convolutional neural network, this paper adopts pulse ...
Wang Chunlin, Tan Kejun
doaj +1 more source