Results 11 to 20 of about 111,958 (254)

FPGAs in The Cloud [PDF]

Computing in Science & Engineering, 2021
As cloud computing grows,  the types of computational hardware available in the cloud are diversifying. Field Programmable Gate Arrays (FPGAs) are a relatively new addition to high-performance computing in the cloud, with the ability to accelerate a range of different applications, and the flexibility to offer different cloud computing models.
Miriam Leeser, Suranga Handagala, Michael Zink, Volodymyr V. Kindratenko, Anne C. Elster   +4 more
openaire   +3 more sources

Application Acceleration on FPGAs with OmpSs@FPGA [PDF]

2018 International Conference on Field-Programmable Technology (FPT), 2018
OmpSs@FPGA is the flavor of OmpSs that allows offloading application functionality to FPGAs. Similarly to OpenMP, it is based on compiler directives. While the OpenMP specification also includes support for heterogeneous execution, we use OmpSs and OmpSs@FPGA as prototype implementation to develop new ideas for OpenMP. OmpSs@FPGA implements the tasking
Bosch, Jaume, Tan, Xubin, Filgueras Izquierdo, Antonio, Vidal, Miquel, Mateu, Marc, Jiménez-González, Daniel, Álvarez, Carlos, Martorell Bofill, Xavier, Ayguadé Parra, Eduard, Labarta Mancho, Jesús José   +9 more
openaire   +3 more sources

Hardware Acceleration of Stochastic Neural Networks Enabled by Bit-Cell Level Co-Design of Magnetic Tunnel Junctions. [PDF]

Adv Sci (Weinh)
An MTJ‐based probabilistic processing‐in‐memory architecture unites nonvolatile storage, local entropy generation, and stochastic computation within each memory cell. Stored multi‐bit weights are converted directly into programmable stochastic bitstreams, enabling neural‐network inference, adaptive Ising optimization, and uncertainty‐aware Bayesian ...
Wang Q, Koh D, McGoldrick B, Mocioi T, Fan Y, Baldo M, Liu L.   +6 more
europepmc   +2 more sources

Hardware‐Native Gaussian Sampling With Probabilistic Ising Machines for Modern Communication Paradigms [PDF]

Advanced science
Probabilistic Ising machines are introduced as hardware‐native Gaussian samplers for edge communication workloads. Tunable variance and sampling density enable accurate distributions for Falcon‐class post‐quantum signatures and diffusion‐based semantic communication.
Rodrigues D, Grimaldi A, Volpe D, Bao Y, Yang S, Grassucci E, Siracusano G, Chiappini M, Carpentieri M, Yang H, Finocchio G.   +10 more
europepmc   +2 more sources

Secure acceleration on cloud-based FPGAs -- FPGA enclaves [PDF]

2020 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), 2020
FPGAs are becoming a common sight in cloud environments and new usage paradigms, such as FPGA-as-a-Service, have emerged. This development poses a challenge to traditional FPGA security models, as these are assuming trust between the user and the hardware owner.
Niklas Lindskog, Håkan Englund
openaire   +1 more source

REFRESH FPGAs: Sustainable FPGA Chiplet Architectures

Proceedings of the 14th International Green and Sustainable Computing Conference, 2023
There is a growing call for greater amounts of increasingly agile computational power for edge and cloud infrastructure to serve the computationally complex needs of ubiquitous computing devices. Thus, an important challenge is addressing the holistic environmental impacts of these next-generation computing systems.
Peipei Zhou 0001, Jinming Zhuang, Stephen Cahoon, Yue Tang 0002, Zhuoping Yang, Xingzhen Chen, Yiyu Shi 0001, Jingtong Hu, Alex K. Jones   +8 more
openaire   +4 more sources

Effects of FPGA architecture on FPGA routing [PDF]

Proceedings of the 32nd ACM/IEEE conference on Design automation conference - DAC '95, 1995
Although many traditional Mask Programmed Gate Array (MPGA) algorithms can be applied to FPGA routing, FPGA architectures impose critical constraints and provide alternative views of the routing problem that allow innovative new algorithms to be applied.
openaire   +1 more source

DP‐FPGA: An FPGA Architecture Optimized for Datapaths [PDF]

VLSI Design, 1996
This paper presents a new Field‐Programmable Gate Array (FPGA) architecture which reduces the density gap between FPGAs and Mask‐Programmed Gate Arrays (MPGAs) for datapath oriented circuits. This is primarily achieved by operating on data as a number of identically programmed four‐bit slices.
Cherepacha, Don, Lewis, David
openaire   +3 more sources

Design of FPGA online loading based on Flash controller

Dianzi Jishu Yingyong, 2019
Traditional way of FPGA configuration file update is using development tools to write FPGA target code to storage devices such as Nor Flash through the JTAG way.However,when the system becomes complicated with multiple FPGA,it takes a long time to update
Lin Tianjing, Ruan Xiang, Liu Chun
doaj   +1 more source

Implementation and applications of tri-state self organising maps on FPGA [PDF]

, 2012
This is the post-print version of the Article. The official published version can be accessed from the link below - Copyright @ 2012 IEEEThis paper introduces a tri-state logic self-organizing map (bSOM) designed and implemented on a field programmable ...
Meng, Hongying, Hunter, A, Dickinson, Patrick, Meng, H, Appiah, Kofi, Appiah, K, Hunter, Andrew, Dickinson, P   +7 more
core   +1 more source