Results 21 to 30 of about 14,564 (222)
Hardware acceleration of number theoretic transform for zk‐SNARK
Engineering Reports, EarlyView., 2023 An FPGA‐based hardware accelerator with a multi‐level pipeline is designed to support the large‐bitwidth and large‐scale NTT tasks in zk‐SNARK. It can be flexibly scaled to different scales of FPGAs and has been equipped in the heterogeneous acceleration system with the help of HLS and OpenCL.
Haixu Zhao +6 more
wiley +1 more source
Real time implementation of separating overlapped algorithm for dual array ADS-B signal
Dianzi Jishu Yingyong, 2020 In order to solve the problem of signal overlapping when communicating in ADS-B system, combined with the working characteristics of FPGA and the requirements of real-time system, the ADS-B overlapping detection algorithm and separating overlapped ...
Hu Tieqiao, Han Bin
doaj +1 more source
Hardware design of convolution calculation module based on systolic array
Dianzi Jishu Yingyong, 2020 Aiming at the long broadcast, much fan in/fan out data path problem brought by high parullelism in the process of the Field Programmable Gate Array(FPGA) to realize the convolution computation in convolutional neural network, this paper adopts pulse ...
Wang Chunlin, Tan Kejun
doaj +1 more source
Design and implementation of dark channel white balance algorithm based on FPGA
Dianzi Jishu Yingyong, 2021 In order to ensure the real-time performance of the system and solve the problem that the perfect reflection method fails in the exposure environment, this paper proposes an FPGA-based dark channel automatic white balance correction algorithm.
Wang Chao, Zhen Guoyong, Shan Yanhu
doaj +1 more source
Design and implementation of HIAF-Kicker power supply communication system
He jishu, 2021 BackgroundIn the injection and extraction Kicker power supply system of High Intensity Heavy-ion Accelerator Facility (HIAF), the transmission efficiency and stability of the control event directly affect the working performance of the power supply ...
LIU Yan +7 more
doaj +1 more source
Realization of SRRC filter and multi-rate conversion based on FPGA
Dianzi Jishu Yingyong, 2018 In order to eliminate the inter symbol interference(ISI) in the communication system and improve the band utilization, the square root-raised cosine filter is often used to realize the base-band shaping filter of the baseband signal.
Yang Yang +3 more
doaj +1 more source
Software-defined protocol independent parser based on FPGA
网络与信息安全学报, 2020 With the boom of information technology, heterogeneous networks with various functions emerge in endlessly, heterogeneous fusion network has become the inevitable trend of the development of the next generation network.
MIAO Lixin, LIU Qinrang, WANG Xin
doaj +1 more source
Journal of Applied Science and Engineering, 2021 Automatic License Plate Recognition (ALPR) systems have become popular application areas of the Internet of Things (IoT). A typical ALPR system always needs powerful processors such as Cortex-A7.
Shizhen Huang +5 more
doaj +1 more source
Comparison of neutron/gamma separation qualities of various organic scintillation materials [PDF]
EPJ Web of Conferences, 2020 In this work we compare the pulse-shape discrimination (PSD) properties of EJ-299-33A, BC-501A, stilbene, p-terphenyl and Hidex Aqualight in neutron field generated by the LVR-15 reactor with silicon filter utilization.
Matěj Zdeněk +8 more
doaj +1 more source
Advanced Materials Technologies, EarlyView.In this study, we propose a biodegradable wireless soil urea sensor for precision agriculture. The sensor's electromagnetic response varies depending on the urea concentration, allowing the measurement of relative soil urea concentrations by analyzing the time‐transient electromagnetic response.
Yu Tanaami +5 more
wiley +1 more source