Results 231 to 240 of about 245,820 (308)

A Rate-Adaptive MAC Protocol for Flexible OFDM-PONs. [PDF]

Sensors (Basel)
Zheng Z, Chi Y, Wang X, Zhang J.
europepmc   +1 more source

DA-FIS: A high-speed dynamic adaptive fault injection server framework for reliable FPGA-based embedded systems. [PDF]

PeerJ Comput Sci
Alhayan F, Kaur G, Alanazi S, Rehman MB, Mansouri W, Albalawneh D, Alqazzaz A, Alkhudhayr H.   +7 more
europepmc   +1 more source

Regular fabric design with ambipolar CNTFETs for FPGA and structured ASIC applications

, 2010
Michele De Marchi, M. Haykel Ben Jamaa, Giovanni De Micheli   +2 more
openalex   +2 more sources

Reduction Method for a Network-on-Chip Low-Level Modeling. [PDF]

Micromachines (Basel)
Lezhnev EV, Romanov AY, Telpukhov DV, Solovyev RA, Romashikhin MY.   +4 more
europepmc   +1 more source

Time and Space Redundancy Fault Tolerance Trade-offs for FPGA Based Single and Multicore Designs

, 2014
Mohamed Ibrahim, Kenichi Asami, Mengu Cho   +2 more
openalex   +2 more sources

Pushing the boundary of quantum advantage in hard combinatorial optimization with probabilistic computers. [PDF]

Nat Commun
Chowdhury S, Aadit NA, Grimaldi A, Raimondo E, Raut A, Lott PA, Mentink JH, Rams MM, Ricci-Tersenghi F, Chiappini M, Theogarajan LS, Srimani T, Finocchio G, Mohseni M, Camsari KY.   +14 more
europepmc   +1 more source

FPGA Implementation of a CNN-Based Topological Trigger for HL-LHC. [PDF]

Comput Softw Big Sci
Brooke J, Clement E, Glowacki M, Paramesvaran S, Segal J.   +4 more
europepmc   +1 more source

Floquet topological states in time-varying metasurfaces. [PDF]

Sci Adv
Ma Q, You JW, Chen L, Gu Z, Qin SL, Lan Z, Cui TJ.   +6 more
europepmc   +1 more source

The Compact Dual Ion Composition Experiment (CoDICE) for the IMAP Mission. [PDF]

Space Sci Rev
Livi SA, Desai MI, Ogasawara K, Kistler L, Möbius E, Starkey MJ, Dayeh MA, Kataria D, Elliott HA, Hart S, Alterman B, McComas DJ, Pollock CJ, Mukherjee J, Trevino J, Ferrell S, Brenner T, Pope SE, Tapley M, Pavlas K, Rankin JS, Shen MM, Khoo L, Alimaganbetov M, Teifert J, Roemer EM, Shaw-Lecerf M, Escobar J, Christian ER, Schwadron NA, Gkioulidou M, Grubbs G, Brysch M, Epperly M, George D, Dunn G, Ford J, Schwendeman CL, Commons M, Persyn S, Jaskulek S, Weidner S, Bert C, Ferris M, Rodriguez B, Nunez C, Urdiales C, Cortinas S, Rodriguez H.   +48 more
europepmc   +1 more source

Hardware implementation of FPGA-based spiking attention neural network accelerator. [PDF]

PeerJ Comput Sci
Geng S, Wang Z, Liu Z, Zhang M, Zhu X, Dan Y.   +5 more
europepmc   +1 more source