Results 21 to 30 of about 232,466 (264)
Constructing cluster of simple FPGA boards for cryptologic computations [PDF]
, 2012 In this paper, we propose an FPGA cluster infrastructure, which can be utilized in implementing cryptanalytic attacks and accelerating cryptographic operations.
Doroz, Yarkin +3 more
core +1 more source
, 2020 AbstractChapter 17 raises considerations to keep in mind when targeting FPGAs using C++ with SYCL. It describes mappings from device code to FPGA devices, how FPGA software and hardware execute a SYCL application, and tips and techniques to keep in mind when writing and optimizing parallel kernels for an FPGA.
Michael Kinsner +5 more
openaire +1 more source
Automatika, 2020 This paper discusses the hardware and control system design of the asymmetric cascade multilevel inverter. The asymmetric cascaded multilevel inverter structure is adopted to minimize bridges, gate drive circuits and DC power source number.
Lazhar Manai, Faouzi Armi, Mongi Besbes
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Effects of FPGA architecture on FPGA routing [PDF]
Proceedings of the 32nd ACM/IEEE conference on Design automation conference - DAC '95, 1995 Although many traditional Mask Programmed Gate Array (MPGA) algorithms can be applied to FPGA routing, FPGA architectures impose critical constraints and provide alternative views of the routing problem that allow innovative new algorithms to be applied.
openaire +2 more sources
Secure acceleration on cloud-based FPGAs – FPGA enclaves [PDF]
2020 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), 2020 FPGAs are becoming a common sight in cloud<br>environments and new usage paradigms, such as FPGA-as-a-Service, have emerged. This development poses a challenge to traditional FPGA security models, as these are assuming trust between the user and the hardware owner.
Håkan Englund, Niklas Lindskog
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Dynamic reconfiguration technologies based on FPGA in software defined radio system [PDF]
, 2011 Partial Reconfiguration (PR) is a method for Field Programmable Gate Array (FPGA) designs which allows multiple applications to time-share a portion of an FPGA while the rest of the device continues to operate unaffected.
Ke He +3 more
core +2 more sources
Motorcycle detection based on deep learning implemented on FPGA [PDF]
Songklanakarin Journal of Science and Technology (SJST), 2021 This paper proposes a hardware accelerator design for motorcycle detection based on deep learning. We designed the training parameters by K-means algorithm and created the motorcycle dataset from Thailand's urban scene.
Feng Peng +3 more
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Research on the method of fast inverse realisation of Vandermonde matrix based on FPGA
The Journal of Engineering, 2019 With the rapid development of science and technology, the operation and calculation in synthetic aperture radar (SAR) imaging systems require high throughput, and the system has high requirement for real-time performance.
Lei Chen, Liang Chen, BingY Li
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FPGA Verification Module [PDF]
Annals of Computer Science and Information Systems, 2014 This paper addresses verification and debugging tool for development of FPGA modules. Proposed tool is developed for educational purposes in teaching students on Digital Design and VHDL programming language. Main goal of the debugging module is to get/set signal values while the FPGA board is running the module of interest.
Zeljko Hocenski, Ivan Aleksi
openaire +5 more sources
Sparse and dense matrix multiplication hardware for heterogeneous multi-precision neural networks
Array, 2021 In this paper, we present hardware accelerators created with high-level synthesis techniques for sparse and dense matrix multiplication operations. The cores can operate with different precisions and are designed to be integrated in a heterogeneous CPU ...
Jose Nunez-Yanez, Mohammad Hosseinabady
doaj