Results 21 to 30 of about 173,842 (233)
SVITE: A Spike-Based VITE Neuro-Inspired Robot Controller [PDF]
, 2013 This paper presents an implementation of a neuro-inspired algorithm called VITE (Vector Integration To End Point) in FPGA in the spikes domain. VITE aims to generate a non-planned trajectory for reaching tasks in robots. The algorithm has been adapted
Domínguez Morales, Manuel Jesús +4 more
core +1 more source
Automatika, 2020 This paper discusses the hardware and control system design of the asymmetric cascade multilevel inverter. The asymmetric cascaded multilevel inverter structure is adopted to minimize bridges, gate drive circuits and DC power source number.
Lazhar Manai, Faouzi Armi, Mongi Besbes
doaj +1 more source
High Throughput Implementation of the Keccak Hash Function Using the Nios-II Processor
Technologies, 2020 Presently, cryptographic hash functions play a critical role in many applications, such as digital signature systems, security communications, protocols, and network security infrastructures.
Argyrios Sideris +2 more
doaj +1 more source
Throughput analysis for a high-performance FPGA-accelerated real-time search application [PDF]
, 2012 We propose an FPGA design for the relevancy computation part of a high-throughput real-time search application. The application matches terms in a stream of documents against a static profile, held in off-chip memory.
Chalamalasetti, S.R. +2 more
core +3 more sources
Low-Power Pedestrian Detection System on FPGA
Proceedings, 2019 Pedestrian detection is one of the key problems in the emerging self-driving car industry. In addition, the Histogram of Gradients (HOG) algorithm proved to provide good accuracy for pedestrian detection.
Vinh Ngo +4 more
doaj +1 more source
FPGA-based heterogeneous acceleration study for multidimensional cubing [PDF]
ITM Web of Conferences, 2022 Today’s information processing not only faces an explosion of data volume and data dimensions, but also has to meet the growing user requirements for timeliness.
Meng Yuan, Yang Jun, Li Jun
doaj +1 more source
Performance comparison of single-precision SPICE Model-Evaluation on FPGA, GPU, Cell, and multi-core processors [PDF]
, 2009 Automated code generation and performance tuning techniques for concurrent architectures such as GPUs, Cell and FPGAs can provide integer factor speedups over multi-core processor organizations for data-parallel, floating-point computation in SPICE model-
DeHon, André, Kapre, Nachiket
core +2 more sources
Motorcycle detection based on deep learning implemented on FPGA [PDF]
Songklanakarin Journal of Science and Technology (SJST), 2021 This paper proposes a hardware accelerator design for motorcycle detection based on deep learning. We designed the training parameters by K-means algorithm and created the motorcycle dataset from Thailand's urban scene.
Feng Peng +3 more
doaj +1 more source
SoPC-based DMA for PCI Express DAQ Cards [PDF]
International Journal of Electronics and Telecommunications, 2021 This paper presents low-cost, configurable PCI Express (PCIe) direct memory access (DMA) interface for implementation on Intel Cyclone V FPGAs. The DMA engine was designed to support DAQ tasks including pre-triggering acquisition for transient analysis ...
Krzysztof Mroczek
doaj +1 more source
MP-STREAM: A Memory Performance Benchmark for Design Space Exploration on Heterogeneous HPC Devices [PDF]
, 2018 Sustained memory throughput is a key determinant of performance in HPC devices. Having an accurate estimate of this parameter is essential for manual or automated design space exploration for any HPC device.
Nabi, Syed Waqar, Vanderbauwhede, Wim
core +1 more source