An Experimental Study of Reduced-Voltage Operation in Modern FPGAs for Neural Network Acceleration [PDF]
, 2020 We empirically evaluate an undervolting technique, i.e., underscaling the circuit supply voltage below the nominal level, to improve the power-efficiency of Convolutional Neural Network (CNN) accelerators mapped to Field Programmable Gate Arrays (FPGAs).
Ergin, Oguz +8 more
core +2 more sources
MP-STREAM: A Memory Performance Benchmark for Design Space Exploration on Heterogeneous HPC Devices [PDF]
, 2018 Sustained memory throughput is a key determinant of performance in HPC devices. Having an accurate estimate of this parameter is essential for manual or automated design space exploration for any HPC device.
Nabi, Syed Waqar, Vanderbauwhede, Wim
core +1 more source
Predictive control using an FPGA with application to aircraft control [PDF]
, 2013 Alternative and more efficient computational methods can extend the applicability of MPC to systems with tight real-time requirements. This paper presents a “system-on-a-chip” MPC system, implemented on a field programmable gate array (FPGA), consisting ...
Constantinides, GA +5 more
core +1 more source
LEGaTO: first steps towards energy-efficient toolset for heterogeneous computing [PDF]
, 2018 LEGaTO is a three-year EU H2020 project which started in December 2017. The LEGaTO project will leverage task-based programming models to provide a software ecosystem for Made-in-Europe heterogeneous hardware composed of CPUs, GPUs, FPGAs and dataflow ...
Alvarez, Carlos +38 more
core +1 more source
Exploiting partial reconfiguration through PCIe for a microphone array network emulator [PDF]
, 2018 The current Microelectromechanical Systems (MEMS) technology enables the deployment of relatively low-cost wireless sensor networks composed of MEMS microphone arrays for accurate sound source localization.
Braeken, An +3 more
core +2 more sources
PGPG: An Automatic Generator of Pipeline Design for Programmable GRAPE Systems [PDF]
, 2007 We have developed PGPG (Pipeline Generator for Programmable GRAPE), a software which generates the low-level design of the pipeline processor and communication software for FPGA-based computing engines (FBCEs).
Fukushige, Toshiyuki +2 more
core +2 more sources
An Efficient and Cost Effective FPGA Based Implementation of the Viola-Jones Face Detection Algorithm [PDF]
, 2017 We present an field programmable gate arrays (FPGA) based implementation of the popular Viola-Jones face detection algorithm, which is an essential building block in many applications such as video surveillance and tracking.
Ababei, Cristinel +4 more
core +4 more sources
Scalability of spin FPGA: A Reconfigurable Architecture based on spin MOSFET
, 2011 Scalability of Field Programmable Gate Array (FPGA) using spin MOSFET (spin FPGA) with magnetocurrent (MC) ratio in the range of 100% to 1000% is discussed for the first time. Area and speed of million-gate spin FPGA are numerically benchmarked with CMOS
Gao Y. +11 more
core +1 more source
Design exploration and performance strategies towards power-efficient FPGA-based achitectures for sound source localization [PDF]
, 2019 Many applications rely on MEMS microphone arrays for locating sound sources prior to their execution. Those applications not only are executed under real-time constraints but also are often embedded on low-power devices.
Braeken, An +4 more
core +1 more source
Possibilities of using of hardware accelerators for intrusion detection and prevention systems
Авіаційно-космічна техніка та технологіяThe subject of this study is the capabilities of FPGA technology for cybersecurity solutions with the network interface accelerators of SmartNIC, as well as the technologies for building, deploying, supporting, and accelerating intrusion detection ...
Artem Tetskyi, Artem Perepelitsyn
doaj +1 more source