Results 31 to 40 of about 162,617 (53)
Self-Partial and Dynamic Reconfiguration Implementation for AES using FPGA [PDF]
, 2009 This paper addresses efficient hardware/software implementation approaches for the AES (Advanced Encryption Standard) algorithm and describes the design and performance testing algorithm for embedded system.
Alaoui Ismaili, Zine El Abidine +1 more
core +1 more source
Using FPGA for visuo-motor control with a silicon retina and a humanoid robot [PDF]
, 2007 The address-event representation (AER) is a neuromorphic communication protocol for transferring asynchronous events between VLSI chips. The event information is transferred using a high speed digital parallel bus.
Delbrück, T. +4 more
core
An Intermediate Language and Estimator for Automated Design Space Exploration on FPGAs
, 2015 We present the TyTra-IR, a new intermediate language intended as a compilation target for high-level language compilers and a front-end for HDL code generators.
Nabi, Syed Waqar, Vanderbauwhede, Wim
core
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Trust in FPGA-accelerated Cloud Computing
ACM Computing Surveys, 2021Furkan Turan, Ingrid M Verbauwhede
exaly
FPGA HLS Today: Successes, Challenges, and Opportunities
ACM Transactions on Reconfigurable Technology and Systems, 2022Jason Cong, Jason Lau, Gai Liu
exaly
A Survey of FPGA-Based LDPC Decoders
IEEE Communications Surveys and Tutorials, 2016Peter Hailes +2 more
exaly
Reconfigurable generic FPGA implementation of fuzzy logic controller for MPPT of PV systems
Renewable and Sustainable Energy Reviews, 2018Ayman Youssef +2 more
exaly
Recent Developments and Challenges in FPGA-Based Time-to-Digital Converters
IEEE Transactions on Instrumentation and Measurement, 2019Rui Machado +2 more
exaly
A PUF-FSM Binding Scheme for FPGA IP Protection and Pay-Per-Device Licensing
IEEE Transactions on Information Forensics and Security, 2015jiliang zhang, Yongqiang Lyu, Gang Qu
exaly