Results 231 to 240 of about 2,991,488 (293)
Development of Channelized K/V Band Dicke Microwave Radiometer Based on SDR. [PDF]
Sensors (Basel)Liang Z, Guo W, Wang C, Liu P, Yang S.
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Multi-stage decimation with hybrid CIC-polyphase filtering for IoT gateway sample rate conversion. [PDF]
Sci RepPinjerla S, Rao SS, Reddy PC.
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Generic logic block based on bias-gated 2D MoS<sub>2</sub> transistors. [PDF]
Nat CommunWei X +10 more
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From pixels to perception: A benchmark for human-like symmetry detection.
Vision ResMuradás Odriozola G +3 more
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A high-frequency decimal multiplier
IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings., 2004Decimal arithmetic is regaining popularity in the computing community due to the growing importance of commercial, financial, and Internet-based applications, which process decimal data. This paper presents an iterative decimal multiplier, which operates at high clock frequencies and scales well to large operand sizes. The multiplier uses a new decimal
Robert D. Kenney +2 more
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Electrical Engineering, 1962
A novel arrangement of n transformers delivers power at n times the line frequency. Ratings compare with transformers of the same weight. Waveform and voltage regulation are excellent. An experimental 7X unit with 60-cycle input gave 3.6 kw of 420-cycle output at approximately 90% efficiency. An additional 5X stage gave 2,100 cycles.
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A novel arrangement of n transformers delivers power at n times the line frequency. Ratings compare with transformers of the same weight. Waveform and voltage regulation are excellent. An experimental 7X unit with 60-cycle input gave 3.6 kw of 420-cycle output at approximately 90% efficiency. An additional 5X stage gave 2,100 cycles.
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Programmable Digital Frequency Multiplier
20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07), 2007A programmable digital frequency multiplier with wide multiplication factor range and low lock time is presented. A digital algorithm is used to generate output frequency and an inbuilt PVT compensation mechanism ensures good frequency stability if there is any change in voltage and temperature during circuit operation. The circuit has been designed in
Sanjay Kumar Wadhwa +2 more
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Frequency Multipliers—An Overview and A 10.5 GHz Frequency Multiplier on TFG Substrate
IETE Technical Review, 1992Most microwave engineers picture a coaxial cavity as a bulky construction, difficult to design at microwave frequencies. This paper demonstrates that multipliers at microwave frequencies can be designed by using microstripline techniques with normally used Teflon Fibre Glass substrates.
D V Ramana +4 more
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IEE-IERE Proceedings - India, 1971
Design details and perfomance of a 2–4 GHz doubler using a disk seal triode is presented. The tube is mounted on the central conductor of a 3λ/4 resonator at the anode. The 2GHz input is applied, through a capacity probe, to another 3λ/4 resonator tuning the cathode. The resonators are built around the tube and are tunable over a small range.
B.M. Banerjee +2 more
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Design details and perfomance of a 2–4 GHz doubler using a disk seal triode is presented. The tube is mounted on the central conductor of a 3λ/4 resonator at the anode. The 2GHz input is applied, through a capacity probe, to another 3λ/4 resonator tuning the cathode. The resonators are built around the tube and are tunable over a small range.
B.M. Banerjee +2 more
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Tristron- a frequency multiplier
International Conference on Actual Problems of Electron Devices Engineering, 2004. APEDE 2004., 2005Investigation of harmonics of a current in tristron is executed by numerical modelling. It is shown, that tristron can be an effective frequency multiplier. Designing of tristron on frequency of 2450 MHz with electronic efficiency of 60 percent is executed.
V.K. Fedyaev, V.N. Kozlov, A.V. Chubenko
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