Results 171 to 180 of about 107,683 (215)
Monolithically integrated solid-state vertical organic electrochemical transistors switching between neuromorphic and logic functions. [PDF]
Sci AdvLi T +5 more
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Gallium Nitride High Electron Mobility Transistor Device with Integrated On-Chip Array Junction Temperature Monitoring Unit. [PDF]
Micromachines (Basel)Chang Y +5 more
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Controllable synthesis of nonlayered high-κ Mn3O4 single-crystal thin films for 2D electronics. [PDF]
Nat CommunYuan J +12 more
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IEEE Journal of Solid-State Circuits, 1982
Combining an advanced 2-/spl mu/m CMOS technology with a newly developed triple-level metallization technology, a high-performance 20K-gate CMOS gate array has been developed. The advantage of triple-level metallization for area saving in a large-scale gate array was evaluated by a computer simulation. The typical gate delay is 1.5 ns with fan-out of 3,
T. Saigo +6 more
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Combining an advanced 2-/spl mu/m CMOS technology with a newly developed triple-level metallization technology, a high-performance 20K-gate CMOS gate array has been developed. The advantage of triple-level metallization for area saving in a large-scale gate array was evaluated by a computer simulation. The typical gate delay is 1.5 ns with fan-out of 3,
T. Saigo +6 more
openaire +2 more sources
IEEE Journal of Solid-State Circuits, 1984
The successful design and fabrication of 1050-gate arrays are reported. Chip size is 3.75/spl times/3.75 mm. A basic cell can be programmed as an enhancement/depletion-type DCFL three-input NOR gate. The speed performance was measured at 0.2-mW/gate power dissipation. Unloaded (fanout=1) propagation delay time was 100 ps/gate.
T. Terada +7 more
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The successful design and fabrication of 1050-gate arrays are reported. Chip size is 3.75/spl times/3.75 mm. A basic cell can be programmed as an enhancement/depletion-type DCFL three-input NOR gate. The speed performance was measured at 0.2-mW/gate power dissipation. Unloaded (fanout=1) propagation delay time was 100 ps/gate.
T. Terada +7 more
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Quantum gate arrays as coherent sums over classical logic gate arrays [PDF]
Journal of Physics A: Mathematical and General, 1997 Quantum spin systems may provide physical realizations of quantum gate arrays. It is shown that certain natural unitary time evolution matrices for spin- quantum spins, interpreted in this context as quantum gate arrays, can be represented as coherent sums, with appropriate phases, over classical logic gate arrays, in a direct analogy with the Feynman ...
Bruno Nachtergaele, Vipul Periwal
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Japanese Journal of Applied Physics, 1983
High speed GaAs DCFL gate array consisting of 500 3-INPUT NOR gates, in which 2000 FETs are integrated, has been successfully fabricated by a Pt buried gate planar E/D process technology. Eleven different 15-stage ring oscillators were made on this gate array to investigate the dependence of gate performance on various loading conditions.
Nobuyuki Toyoda +4 more
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High speed GaAs DCFL gate array consisting of 500 3-INPUT NOR gates, in which 2000 FETs are integrated, has been successfully fabricated by a Pt buried gate planar E/D process technology. Eleven different 15-stage ring oscillators were made on this gate array to investigate the dependence of gate performance on various loading conditions.
Nobuyuki Toyoda +4 more
openaire +2 more sources
Field-Programmable Gate Arrays
Communications of the ACM, 1999Field programmable gate arrays (FPGAs) are a flexible alternative to custom integrated circuits. They can implement both combinatorial and sequential logic of tens of thousands of gates. Historically, software has been considered "flexible" with hardware its rigid counterpart in system design.
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1982 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, 1982
This paper will describe a gate array with a loaded propagation delay of 2ns per gate. The device employs 2μm rules, double metal layers, silicon gate technology and bent-gate patterns for a minimum chip area.
M. Asano +8 more
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This paper will describe a gate array with a loaded propagation delay of 2ns per gate. The device employs 2μm rules, double metal layers, silicon gate technology and bent-gate patterns for a minimum chip area.
M. Asano +8 more
openaire +2 more sources
IEEE Journal of Solid-State Circuits, 1984
A method for converting integrated circuit personalizations from a technology providing one set of design rules to a technology with a different and smaller set of design rules is presented. An example showing a conversion to a new technology where the cell area was reduced by 59% and the speed was increased more than 4.0% is illustrated.
K.J. Reasoner, D.W. Still, L.A. Akers
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A method for converting integrated circuit personalizations from a technology providing one set of design rules to a technology with a different and smaller set of design rules is presented. An example showing a conversion to a new technology where the cell area was reduced by 59% and the speed was increased more than 4.0% is illustrated.
K.J. Reasoner, D.W. Still, L.A. Akers
openaire +3 more sources