Results 11 to 20 of about 2,171,560 (236)
Scalable gate architecture for densely packed semiconductor spin qubits [PDF]
, 2016 We demonstrate a 12 quantum dot device fabricated on an undoped Si/SiGe heterostructure as a proof-of-concept for a scalable, linear gate architecture for semiconductor quantum dots.
Hazard, T. M. +4 more
core +2 more sources
A control hardware based on a field programmable gate array for experiments in atomic physics. [PDF]
Review of Scientific Instruments, 2020 Experiments in Atomic, Molecular, and Optical (AMO) physics require precise and accurate control of digital, analog, and radio frequency (RF) signals. We present control hardware based on a field programmable gate array core that drives various modules ...
A. Bertoldi +10 more
semanticscholar +1 more source
Applied Sciences, 2021 The degradation effect of a field-programmable gate array becomes a significant issue due to the high density of logic circuits inside the field-programmable gate array. The degradation effect occurs because of the rapid technology scaling process of the
Anuar Jaafar +4 more
doaj +1 more source
FPGA Implementation of Threshold-Type Binary Memristor and Its Application in Logic Circuit Design
Micromachines, 2021 In this paper, a memristor model based on FPGA (field programmable gate array) is proposed, by using which the circuit of AND gate and OR gate composed of memristors is built. Combined with the original NOT gate in FPGA, the NAND gate, NOR gate, XOR gate
Liu Yang +3 more
doaj +1 more source
Amorphous IGZO Thin-Film Transistor Gate Driver in Array for Ultra-Narrow Border Displays
IEEE Journal of the Electron Devices Society, 2022 A gate driver in array (GIA) design based on the amorphous indium gallium zinc oxide (a-IGZO) thin-film transistor (TFT) is developed for narrow border displays.
Liufei Zhou +6 more
doaj +1 more source
Mixed-precision weights network for field-programmable gate array.
PLoS ONE, 2021 In this study, we introduced a mixed-precision weights network (MPWN), which is a quantization neural network that jointly utilizes three different weight spaces: binary {-1,1}, ternary {-1,0,1}, and 32-bit floating-point.
Ninnart Fuengfusin, Hakaru Tamukoh
doaj +1 more source
Efficient fault-tolerant implementations of non-Clifford gates with reconfigurable atom arrays [PDF]
npj Quantum Information 10, 136 (2024), 2023 To achieve scalable universal quantum computing, we need to implement a universal set of logical gates fault-tolerantly, for which the main difficulty lies with non-Clifford gates. We demonstrate that several characteristic features of the reconfigurable atom array platform are inherently well-suited for addressing this key challenge, potentially ...
arxiv +1 more source
Continuous-Time Programming of Floating-Gate Transistors for Nonvolatile Analog Memory Arrays
Journal of Low Power Electronics and Applications, 2021 Floating-gate (FG) transistors are a primary means of providing nonvolatile digital memory in standard CMOS processes, but they are also key enablers for large-scale programmable analog systems, as well.
Brandon Rumberg +4 more
doaj +1 more source
Adding Binary Numbers with Discrete Solitons in Waveguide Arrays [PDF]
Phys. Scr., 95, 085107 (2020), 2021 We present a design and protocol to add binary numbers using discrete solitons in waveguide arrays. We show that the nonlinear interaction between discrete solitons in waveguide arrays can be exploited to design half and full adders. By modulating the separation between waveguides and introducing control solitons, we achieve the performance of an XOR ...
arxiv +1 more source
The Synthesis Method of Logic Circuits Based on the NMOS-Like RRAM Gates
IEEE Access, 2021 The synthesis method of logic circuits based on the RRAM (Resistive Random Access Memory) devices is of great concern in recent years. Inspired by the CMOS-like RRAM based logic gates, this work proposes a NMOS-like RRAM gate family.
Xiaole Cui, Ye Ma, Feng Wei, Xiaoxin Cui
doaj +1 more source