Results 201 to 210 of about 40,049 (263)

Ferroelectric Optoelectronic Sensor for Intelligent Flame Detection and In-Sensor Motion Perception. [PDF]

open access: yesNanomicro Lett
Wei J   +18 more
europepmc   +1 more source

Programmable Quantum Gate Arrays

Fortschritte der Physik, 2001
Summary: We present a probabilistic quantum processor for qubits. The processor itself is represented by a fixed array of gates. The input of the processor is constituted by two registers. In the program register the set of instructions (program) is encoded. This program is applied to the data register.
Hillery, Mark   +2 more
openaire   +2 more sources

500 Gates GaAs Gate Array

Japanese Journal of Applied Physics, 1983
High speed GaAs DCFL gate array consisting of 500 3-INPUT NOR gates, in which 2000 FETs are integrated, has been successfully fabricated by a Pt buried gate planar E/D process technology. Eleven different 15-stage ring oscillators were made on this gate array to investigate the dependence of gate performance on various loading conditions.
Nobuyuki Toyoda   +4 more
openaire   +1 more source

Molecular Logic Gate Arrays

Chemistry – An Asian Journal, 2011
AbstractChemists are now able to emulate the ideas and instruments of mathematics and computer science with molecules. The integration of molecular logic gates into small arrays has been a growth area during the last few years. The design principles underlying a collection of these cases are examined. Some of these computing molecules are applicable in
openaire   +3 more sources

A 6,000-gate CMOS gate array

1982 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, 1982
This paper will describe a gate array with a loaded propagation delay of 2ns per gate. The device employs 2μm rules, double metal layers, silicon gate technology and bent-gate patterns for a minimum chip area.
T. Itoh   +8 more
openaire   +1 more source

High-Speed MOS Gate Array

IEEE Journal of Solid-State Circuits, 1980
The dimensions of the fundamental gate cell were analyzed in the gate-array type masterslice LSI which utilized the DSA MOS process combined with two-level metallization technology. It was revealed that the optimum gate width was 80 µm in the 4-µm design rule, taking the total power dissipation of 3 W and the delay time below 2 ns into consideration ...
M. Nakaya   +3 more
openaire   +1 more source

Gate array architectures

Microprocessors and Microsystems, 1988
Abstract The gate array approach to semicustom integrated circuit design is described. Traditional architectures are described, followed by some more recent introductions which attempt to eliminate some of the common limitations. Modern sea-of-gates architectures are shown to offer considerable potential.
openaire   +1 more source

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