Results 221 to 230 of about 325,757 (287)

Scanning Tunnelling Microscopy Study of Spin Interactions in Transition‐Metal Phthalocyanine Adsorbates: Mechanisms, Signatures, and Control Strategies

open access: yesAdvanced Science, EarlyView.
Transition‐metal phthalocyanine (TMPc) molecules serve as model systems for probing the spin interactions. This review summarizes recent scanning tunnelling microscopy advances on the spin‐related phenomena in TMPc adsorbates, including Kondo effect, spin excitations, and Yu–Shiba–Rusinov states, emphasizing the mechanisms and control strategies, and ...
Fudi Zhou   +6 more
wiley   +1 more source

Ferroelectric Devices for In‐Memory and In‐Sensor Computing

open access: yesAdvanced Science, EarlyView.
Inspired by biological systems, in‐memory and in‐sensor computing overcome von Neumann bottlenecks. Ferroelectric devices can mimic synaptic functions and sense stimuli like light or force, therefore are ideal for these paradigms. This review introduces the ferroelectric devices applied for in‐memory and in‐sensor computing, covering their structures ...
Hong Fang   +5 more
wiley   +1 more source

Ultrafast visual perception beyond human capabilities enabled by motion analysis using synaptic transistors. [PDF]

open access: yesNat Commun
Wang S   +16 more
europepmc   +1 more source

Owl-vision-inspired near sensor computing. [PDF]

open access: yesNat Commun
Zhao Z   +10 more
europepmc   +1 more source

Radiofrequency cascade readout of coupled spin qubits. [PDF]

open access: yesNat Electron
Chittock-Wood JF   +14 more
europepmc   +1 more source

Robust and localised control of a 10-spin qubit array in germanium. [PDF]

open access: yesNat Commun
John V   +12 more
europepmc   +1 more source
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A subnanosecond 8K-gate CMOS/SOS gate array

IEEE Journal of Solid-State Circuits, 1984
An 8370-gate CMOS/SOS gate array has been developed using a Si-gate CMOS/SOS process with two-level metallization. The gate lengths of the transistors are 1.8 and 1.9 /spl mu/m for the n-channel and p-channel, respectively. Subnanosecond typical gate delay times have been obtained.
K Maeguchi
exaly   +2 more sources

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