Results 241 to 250 of about 325,757 (287)

A reprogrammable gate array and applications

Proceedings of the IEEE, 1993
A field-programmable gate array (FPGA) can implement thousands of gates of logic, has no up-front fixed costs, and can be programmed in a few minutes by writing into on-chip static memory is described. This kind of FPGA can be reprogrammed any number of times, providing a versatile platform for rapid hardware implementation.
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500 Gates GaAs Gate Array

Japanese Journal of Applied Physics, 1983
High speed GaAs DCFL gate array consisting of 500 3-INPUT NOR gates, in which 2000 FETs are integrated, has been successfully fabricated by a Pt buried gate planar E/D process technology. Eleven different 15-stage ring oscillators were made on this gate array to investigate the dependence of gate performance on various loading conditions.
Nobuyuki Toyoda, Toshiyuki Terada, Masao Mochizuki, Katsue Kanazawa, Akimichi Hojo   +4 more
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Gate array layout automation

Proceedings of the ACM '81 conference on - ACM 81, 1981
Gate array layout is becoming an increasingly important topic in design automation, as utilization of these components expands. In this tutorial a model of gate array physical design is first presented, introducing nomenclature used thereafter. The architecture of a typical gate array layout system is briefly discussed, establishing the environmental ...
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A 9000-gate user-programmable gate array

Proceedings of the IEEE 1988 Custom Integrated Circuits Conference, 2003
The 900-gate XC3090 CMOS user-programmable gate array is the largest member of a family of devices based on a second-generation logic cell array (LCA) architecture. This architecture features three types of user-configurable elements: an interior array of logic blocks, a perimeter of input/output (I/O) blocks, and interconnection resources ...
H.-C. Hsieh, K. Dong, J.Y. Ja, R. Kanazawa, L.T. Ngo, L.G. Tinkey, W.S. Carter, R.H. Freeman   +7 more
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Antifuse field programmable gate arrays

Proceedings of the IEEE, 1993
An antifuse is an electrically programmable two-terminal device with small area and low parasitic resistance and capacitance. Field-programmable gate arrays (FPGAs) using antifuses in a segmented channel routing architecture now offer the digital logic capabilities of an 8000-gate conventional gate array and system speeds of 40-60 MHz.
Jonathan Greene, Esmat Hamdy, Sam Beal
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Logic synthesis for programmable gate arrays

Conference proceedings on 27th ACM/IEEE design automation conference - DAC '90, 1990
The problem of combinational logic synthesis is addressed for two interesting and popular classes of programmable gate array architecture: table-lookup and multiplexer-based. The constraints imposed by some of these architectures require new algorithms for minimization of the number of basic blocks of the target architecture, taking into account the ...
Rajeev Murgai, Yoshihito Nishizaki, Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli   +4 more
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Recursive Gate-Arrays

1988
Abstract : The authors propose a regular architecture, called recursive gate- arrays, suitable for circuits with modules of nonuniform size. A set of n (rectangular and L-shaped) modules can be placed in a recursive gate-array. The placement can be obtained in O(n log n) time. Keywords: VLSI layout placement, Knock-knee model.
M. Sarrafzadeh, S. Maddila, C. Chiang
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A Self-Reconfigurable Gate Array Architecture

2000
This paper presents an innovative architecture for a reconfigurable device that allows single cycle context switching and single cycle random access to the unified on-chip configuration/data memory. These two features are necessary for efficient self-reconfiguration and are useful in general as well--no other device offers both features.
Sidhu, Reetinder, Wadhwa, Sameer, MEI, Alessandro, Prasanna, Viktor K.   +3 more
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A 20K gate CMOS gate array

1983 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, 1983
T. Saigo, H. Tago, M. Shiochi, T. Hiwatashi, S. Shima, T. Moriya   +5 more
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A 6K-gate CMOS gate array

1982 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, 1982
T. Kobayashi, H. Tago, T. Moriya, S. Yamamoto   +3 more
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