Results 231 to 240 of about 325,757 (287)
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A 10K-Gate CMOS Gate Array Based on a Gate Isolation Structure
IEEE Journal of Solid-State Circuits, 1985This paper describes an effect of the "gate isolation" technique and its application to a 10K-gate CMOS gate-array VLSI chip. This gate array is fabricated using a 2-/spl mu/m n-well CMOS technology, with double-level metallization. As an example, a 32-bit parallel array multiplier is designed using a fully automatic CAD system.
K. Sakashita +5 more
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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1984
We propose a new approach to the global routing of gate arrays. The method can handle any channel capacities and pin distributions on the chip. The global router first finds unique routes, then pushes connections to the periphery. As outer wiring capacity is consumed, the routing continues inward, connecting pins and making global cell assignments for ...
Jeong-Tyng Li, Malgorzata Marek-Sadowska
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We propose a new approach to the global routing of gate arrays. The method can handle any channel capacities and pin distributions on the chip. The global router first finds unique routes, then pushes connections to the periphery. As outer wiring capacity is consumed, the routing continues inward, connecting pins and making global cell assignments for ...
Jeong-Tyng Li, Malgorzata Marek-Sadowska
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Programmable Quantum Gate Arrays
Fortschritte der Physik, 2001Summary: We present a probabilistic quantum processor for qubits. The processor itself is represented by a fixed array of gates. The input of the processor is constituted by two registers. In the program register the set of instructions (program) is encoded. This program is applied to the data register.
Hillery, Mark +2 more
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Microprocessors and Microsystems, 1988
Abstract The gate array approach to semicustom integrated circuit design is described. Traditional architectures are described, followed by some more recent introductions which attempt to eliminate some of the common limitations. Modern sea-of-gates architectures are shown to offer considerable potential.
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Abstract The gate array approach to semicustom integrated circuit design is described. Traditional architectures are described, followed by some more recent introductions which attempt to eliminate some of the common limitations. Modern sea-of-gates architectures are shown to offer considerable potential.
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Routing Techniques for Gate Array
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1983This paper describes the routing techniques used for a Hughes internally developed high-density silicon-gate bulk CMOS gate array family. This layout software can be easily adapted to different array sizes and/or technologies (e.g., bipolar) through a change of parameters.
B. S. Ting, Bou Nin Tien
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Proceedings 1988 IEEE International Conference on Computer Design: VLSI, 2003
It is noted that gate arrays have come of age in the 1980s and CMOS is the dominant technology. Major advances in manufacturing, architecture, and integrated CAD (computer-aided design) tools have allowed predictable delivery of circuits with 100000 used gates.
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It is noted that gate arrays have come of age in the 1980s and CMOS is the dominant technology. Major advances in manufacturing, architecture, and integrated CAD (computer-aided design) tools have allowed predictable delivery of circuits with 100000 used gates.
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2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512), 2004
The precision of digital-to-analog converters (DAC) is always limited by element mismatching. These elements can be transistors, resistors, capacitors, etc. Techniques used to improve resolution often involve the sacrifice of die area. In this paper we present a design for a DAC using floating-gate MOS transistors.
Guillermo J. Serrano, Paul E. Hasler
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The precision of digital-to-analog converters (DAC) is always limited by element mismatching. These elements can be transistors, resistors, capacitors, etc. Techniques used to improve resolution often involve the sacrifice of die area. In this paper we present a design for a DAC using floating-gate MOS transistors.
Guillermo J. Serrano, Paul E. Hasler
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Optically reconfigurable gate array
Proceedings 29th Applied Imagery Pattern Recognition Workshop, 2002Summary form only given, as follows. Reconfigurable processors, like the Field Programmable Gate Arrays (FPGAs), open new computational paradigms where the processor is able to tailor its internal structure to better implement a given application. A typical FPGA consists of an array of configurable logic blocks and a mesh of interconnections fully ...
Jose Mumbru +5 more
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1982 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, 1982
This paper will describe a gate array with a loaded propagation delay of 2ns per gate. The device employs 2μm rules, double metal layers, silicon gate technology and bent-gate patterns for a minimum chip area.
T. Itoh +8 more
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This paper will describe a gate array with a loaded propagation delay of 2ns per gate. The device employs 2μm rules, double metal layers, silicon gate technology and bent-gate patterns for a minimum chip area.
T. Itoh +8 more
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Chemistry – An Asian Journal, 2011
AbstractChemists are now able to emulate the ideas and instruments of mathematics and computer science with molecules. The integration of molecular logic gates into small arrays has been a growth area during the last few years. The design principles underlying a collection of these cases are examined. Some of these computing molecules are applicable in
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AbstractChemists are now able to emulate the ideas and instruments of mathematics and computer science with molecules. The integration of molecular logic gates into small arrays has been a growth area during the last few years. The design principles underlying a collection of these cases are examined. Some of these computing molecules are applicable in
openaire +3 more sources