Results 321 to 330 of about 2,178,356 (388)
Microelectronics International, 1988 Software tools are an essential part of any IC design system but there are dangers associated with the introduction of CAD systems. This paper attempts to lift the software cloak which, along with the ubiquitous workstation, tends to cover the finer points of CMOS design.
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Advanced Functional Materials, 2018
The fabrication of a skin‐attachable, stretchable array of high‐sensitivity temperature sensors is demonstrated. The temperature sensor consists of a single‐walled carbon nanotube field‐effect transistor with a suspended gate electrode of poly(N ...
Soo Yeong Hong +9 more
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The fabrication of a skin‐attachable, stretchable array of high‐sensitivity temperature sensors is demonstrated. The temperature sensor consists of a single‐walled carbon nanotube field‐effect transistor with a suspended gate electrode of poly(N ...
Soo Yeong Hong +9 more
semanticscholar +1 more source
1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, 1987
This paper will report on a gate array that employs Schottky diode capacitor-coupled logic to attain a noise margin of 400mV. At a power dissipation of 1mW%gate, the propagation delay was 284ps.
K. Kawakyu +8 more
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This paper will report on a gate array that employs Schottky diode capacitor-coupled logic to attain a noise margin of 400mV. At a power dissipation of 1mW%gate, the propagation delay was 284ps.
K. Kawakyu +8 more
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Routing Techniques for Gate Array
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1983This paper describes the routing techniques used for a Hughes internally developed high-density silicon-gate bulk CMOS gate array family. This layout software can be easily adapted to different array sizes and/or technologies (e.g., bipolar) through a change of parameters.
Bou Nin Tien, B.S. Ting
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Proceedings 1988 IEEE International Conference on Computer Design: VLSI, 2003
It is noted that gate arrays have come of age in the 1980s and CMOS is the dominant technology. Major advances in manufacturing, architecture, and integrated CAD (computer-aided design) tools have allowed predictable delivery of circuits with 100000 used gates.
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It is noted that gate arrays have come of age in the 1980s and CMOS is the dominant technology. Major advances in manufacturing, architecture, and integrated CAD (computer-aided design) tools have allowed predictable delivery of circuits with 100000 used gates.
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Microelectronic Engineering, 2001
Abstract The successful fabrication of field emission (FE) devices is directly related to process simplicity and device performance, which depends to a large extent on the tip material and emitter geometry. On the other hand, these characteristics are the most important issues influencing industrial applicability of the FE devices.
Tomasz Debski +11 more
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Abstract The successful fabrication of field emission (FE) devices is directly related to process simplicity and device performance, which depends to a large extent on the tip material and emitter geometry. On the other hand, these characteristics are the most important issues influencing industrial applicability of the FE devices.
Tomasz Debski +11 more
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ChemInform Abstract: Molecular Logic Gate Arrays
ChemInform, 2011AbstractReview: [167 refs.]
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Hardware acceleration of gate array layout
Proceedings of the 22nd ACM/IEEE conference on Design automation - DAC '85, 1985In this paper we describe the hardware and software of a system which we have implemented to accelerate the physical design of gate arrays. In contrast to nearly all other reported approaches, our approach to hardware acceleration is to augment a single-user host workstation with a general-purpose microprogrammable slave processor having a large ...
Philip M. Spira, Carl Hage
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2nd International Conference on ASIC, 2002
BiCMOS gate array circuits and macrocell libraries are designed and fabricated through 2.0 /spl mu/m BiCMOS standard processes. The average gate delay time is as follows: BiCMOS 21 stage inverter, 1.1 ns; BiCMOS 21 stage oscillator, 1.1 ns; BiCMOS 21 stage NAND, 1.3 ns; BiCMOS 21 stage NOR, 1.4 ns.
Min Zhang, Xuhong Hu, Meiyuan Wang
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BiCMOS gate array circuits and macrocell libraries are designed and fabricated through 2.0 /spl mu/m BiCMOS standard processes. The average gate delay time is as follows: BiCMOS 21 stage inverter, 1.1 ns; BiCMOS 21 stage oscillator, 1.1 ns; BiCMOS 21 stage NAND, 1.3 ns; BiCMOS 21 stage NOR, 1.4 ns.
Min Zhang, Xuhong Hu, Meiyuan Wang
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IEEE Transactions on Components, Hybrids, and Manufacturing Technology, 1982
Because of the increasing complexity of new integrated circuits (IC's) and the limited supply of IC designers, structured design approaches are necessary. A gate array is a common approach to structuring, formalizing, and thus simplifying the design process.
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Because of the increasing complexity of new integrated circuits (IC's) and the limited supply of IC designers, structured design approaches are necessary. A gate array is a common approach to structuring, formalizing, and thus simplifying the design process.
openaire +2 more sources