Results 321 to 330 of about 2,144,818 (365)

Routing Techniques for Gate Array

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1983
This paper describes the routing techniques used for a Hughes internally developed high-density silicon-gate bulk CMOS gate array family. This layout software can be easily adapted to different array sizes and/or technologies (e.g., bipolar) through a change of parameters.
Bou Nin Tien, B.S. Ting
openaire   +1 more source

ChemInform Abstract: Molecular Logic Gate Arrays

ChemInform, 2011
AbstractReview: [167 refs.]
openaire   +5 more sources

Programmable Quantum Gate Arrays

Fortschritte der Physik, 2001
We present a probabilistic quantum processor for qubits. The processor itself is represented by a fixed array of gates. The input of the processor is constituted by two registers. In the program register the set of instructions (program) is encoded. This program is applied to the data register.
Mark Hillery, Vladimír Bužek, Mário Ziman   +2 more
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Hardware acceleration of gate array layout

Proceedings of the 22nd ACM/IEEE conference on Design automation - DAC '85, 1985
In this paper we describe the hardware and software of a system which we have implemented to accelerate the physical design of gate arrays. In contrast to nearly all other reported approaches, our approach to hardware acceleration is to augment a single-user host workstation with a general-purpose microprogrammable slave processor having a large ...
Philip M. Spira, Carl Hage
openaire   +2 more sources

Gated field emitter arrays

Microelectronic Engineering, 2001
Abstract The successful fabrication of field emission (FE) devices is directly related to process simplicity and device performance, which depends to a large extent on the tip material and emitter geometry. On the other hand, these characteristics are the most important issues influencing industrial applicability of the FE devices.
Tomasz Debski, Ivan Kostic, Piotr Grabiec, Steffen Biehl, A. E. Lushkin, Stanislaw Mitura, Peter Hudek, Ivo W. Rangelow, Wolfgang Barth, I. I. Bekh, L. G. Il’chenko, V. V. Il’chenko   +11 more
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BiCMOS gate array circuits

2nd International Conference on ASIC, 2002
BiCMOS gate array circuits and macrocell libraries are designed and fabricated through 2.0 /spl mu/m BiCMOS standard processes. The average gate delay time is as follows: BiCMOS 21 stage inverter, 1.1 ns; BiCMOS 21 stage oscillator, 1.1 ns; BiCMOS 21 stage NAND, 1.3 ns; BiCMOS 21 stage NOR, 1.4 ns.
Min Zhang, Xuhong Hu, Meiyuan Wang
openaire   +2 more sources

Field programmable gate array implementation of space-vector pulse-width modulation technique for five-phase voltage source inverter

, 2014
This study analyses a field programmable gate array (FPGA) implementation of space-vector pulse-width modulation (SVPWM) technique for five-phase voltage source inverter (VSI).
G. Renukadevi, K. Rajambal
semanticscholar   +1 more source

Gate Arrays for VLSI Design

IEEE Transactions on Components, Hybrids, and Manufacturing Technology, 1982
Because of the increasing complexity of new integrated circuits (IC's) and the limited supply of IC designers, structured design approaches are necessary. A gate array is a common approach to structuring, formalizing, and thus simplifying the design process.
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Optically reconfigurable gate array

Proceedings 29th Applied Imagery Pattern Recognition Workshop, 2002
Summary form only given, as follows. Reconfigurable processors, like the Field Programmable Gate Arrays (FPGAs), open new computational paradigms where the processor is able to tailor its internal structure to better implement a given application. A typical FPGA consists of an array of configurable logic blocks and a mesh of interconnections fully ...
Demetri Psaltis, Fai Mok, Gan Zhou, George Panotopoulos, Xin An, Jose Mumbru   +5 more
openaire   +2 more sources

Inkjet-Configurable Gate Array

2018
Over the last decades, Organic Electronics has been emerging as a multidisciplinary and innovative way to generate electronic devices and systems. It is intended to provide a platform for low-cost, large-area, and low-frequency Printable Electronics on a variety of substrates, including flexible plastic substrates.
Lluis Teres, Jordi Carrabina Bordoll, Mohammad Mashayekhi   +2 more
openaire   +2 more sources