Efficient Hardware Accelerator Design of Non-Linear Optimization Correlative Scan Matching Algorithm in 2D LiDAR SLAM for Mobile Robots [PDF]
Simultaneous localization and mapping (SLAM) is the major solution for constructing or updating a map of an unknown environment while simultaneously keeping track of a mobile robot’s location.
Ao Hu +9 more
doaj +4 more sources
Low power reprogrammable DNA basecaller with an efficient HMM accelerator for real time nanopore sequencing [PDF]
Basecalling is a crucial step in DNA sequencing that converts raw nanopore signals into nucleotide sequences. This paper presents a serial-parallel reprogrammable DNA sequencing accelerator based on a 64-state Hidden Markov Model (HMM) implemented in a ...
Atefeh Salimi Shahraki +3 more
doaj +2 more sources
Accelerating hybrid XOR–CNF Boolean satisfiability problems natively with in-memory computing [PDF]
The Boolean satisfiability (SAT) problem is a computationally challenging decision problem central to many industrial applications. For SAT problems in cryptanalysis, circuit design, and telecommunication, solutions can often be found more efficiently by
Haesol Im +16 more
doaj +2 more sources
Deployment and validation of predictive 6-dimensional beam diagnostics through generative reconstruction with standard accelerator elements [PDF]
Understanding the 6-dimensional phase space distribution of particle beams is essential for optimizing accelerator performance. Conventional diagnostics such as use of transverse deflecting cavities offer detailed characterization but require dedicated ...
Seongyeol Kim +9 more
doaj +2 more sources
Single-Image Visibility Restoration: A Machine Learning Approach and Its 4K-Capable Hardware Accelerator [PDF]
Dat Ngo, Seungmin Lee, Gi-Dong Lee
exaly +2 more sources
Consumer Document Analytical Accelerator Hardware
Document scanning devices are used for visual character recognition, followed by text analytics in the software. Often such character extraction is insecure, and any third party can manipulate the information.
Aswani Radhakrishnan +2 more
doaj +1 more source
This paper proposes both software and hardware mechanisms based on the near-memory processing (NMP) accelerator to improve the linked list traversal of the in-memory caching.
Minkwan Kee, Chiwon Han, Gi-Ho Park
doaj +1 more source
Polynomial multiplication is one of the heaviest operations for a lattice-based public key algorithm in Post-Quantum Cryptography (PQC). Many studies have been done to accelerate polynomial multiplication with newly developed hardware accelerators or ...
Jong-Yeon Park +4 more
doaj +1 more source
An OpenCL-Based FPGA Accelerator for Faster R-CNN
In recent years, convolutional neural network (CNN)-based object detection algorithms have made breakthroughs, and much of the research corresponds to hardware accelerator designs. Although many previous works have proposed efficient FPGA designs for one-
Jianjing An +3 more
doaj +1 more source
CORDIC Hardware Acceleration Using DMA-Based ISA Extension
The use of RISC-based embedded processors aimed at low cost and low power is becoming an increasingly popular ecosystem for both hardware and software development. High-performance yet low-power embedded processors may be attained via the use of hardware
Erez Manor +2 more
doaj +1 more source

