Results 21 to 30 of about 717,844 (304)
Hardware Acceleration of Sparse Oblique Decision Trees for Edge Computing
Elektronika ir Elektrotechnika, 2019 This paper presents a hardware accelerator for sparse decision trees intended for FPGA applications. To the best of authors’ knowledge, this is the first accelerator of this type. Beside the hardware accelerator itself, a novel algorithm for induction of
Predrag Teodorovic +1 more
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Differentiable Neural Architecture, Mixed Precision and Accelerator Co-Search
IEEE Access, 2023 Quantization, effective Neural Network architecture, and efficient accelerator hardware are three important design paradigms to maximize accuracy and efficiency.
Krishna Teja Chitty-Venkata +4 more
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Multi-engine packet classification hardware accelerator [PDF]
, 2009 As line rates increase, the task of designing high performance architectures with reduced power consumption for the processing of router traffic remains important. In this paper, we present a multi-engine packet classification hardware accelerator, which
Wang, Xiaojun +7 more
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Proceedings of the Genetic and Evolutionary Computation Conference Companion, 2022 Evolutionary computation has been shown to be a highly effective method for training neural networks, particularly when employed at scale on CPU clusters. Recent work have also showcased their effectiveness on hardware accelerators, such as GPUs, but so far such demonstrations are tailored for very specific tasks, limiting applicability to other ...
Yujin Tang, Yingtao Tian, David Ha
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A High-Performance Multimem SHA-256 Accelerator for Society 5.0
IEEE Access, 2021 The development of a low-cost high-performance secure hash algorithm (SHA)-256 accelerator has recently received extensive interest because SHA-256 is important in widespread applications, such as cryptocurrencies, data security, data integrity, and ...
Thi Hong Tran +2 more
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Design of a BP neural network SoC based on domestic embedded CPU
Dianzi Jishu Yingyong, 2021 The paper designs a Back Propagation(BP)neural network system on chip(SoC) based on the domestic embedded Central Processing Unit(CPU) CK803S and its SoC design platform.
Xu Wenliang
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FPGA Implementation of A∗ Algorithm for Real-Time Path Planning
International Journal of Reconfigurable Computing, 2020 The traditional A∗ algorithm is time-consuming due to a large number of iteration operations to calculate the evaluation function and sort the OPEN list.
Yuzhi Zhou, Xi Jin, Tianqi Wang
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Convolution Neural Network Hardware Accelerator [PDF]
, 2022 This project aims to develop and test a Hardware Accelerator for a Convolutional Neural Network capable of analyzing handwritten digits. Convolutional neural networks can be defined as neural networks which make use of perceptrons for supervised learning.
Khan, Afwan
core
, 2023 This paper presents the Instruction-Level Abstraction (ILA) as a formal software/hardware interface for accelerator-rich platforms. The ILA provides a common framework for formal functional specification of processors and accelerator behavior, verifying ...
Zhang, Hongce +3 more
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Alexandria Engineering Journal, 2022 Adoption of IoT technology without considering its security implications may expose network systems to a variety of security breaches. In network systems, IoT edge devices are a major source of security risks.
Atef Ibrahim, Fayez Gebali
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