Results 21 to 30 of about 77,762 (283)
Hardware-accelerated dynamic binary translation [PDF]
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017, 2017 Dynamic Binary Translation (DBT) is often used in hardware/software co-design to take advantage of an architecture model while using binaries from another one. The co-development of the DBT engine and of the execution architecture leads to architecture with special support to these mechanisms.
Rokicki, Simon +2 more
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Hardware Acceleration of Sparse Oblique Decision Trees for Edge Computing
Elektronika ir Elektrotechnika, 2019 This paper presents a hardware accelerator for sparse decision trees intended for FPGA applications. To the best of authors’ knowledge, this is the first accelerator of this type. Beside the hardware accelerator itself, a novel algorithm for induction of
Predrag Teodorovic +1 more
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Differentiable Neural Architecture, Mixed Precision and Accelerator Co-Search
IEEE Access, 2023 Quantization, effective Neural Network architecture, and efficient accelerator hardware are three important design paradigms to maximize accuracy and efficiency.
Krishna Teja Chitty-Venkata +4 more
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Resistive Neural Hardware Accelerators
Proceedings of the IEEE, 2023 Deep Neural Networks (DNNs), as a subset of Machine Learning (ML) techniques, entail that real-world data can be learned and that decisions can be made in real-time. However, their wide adoption is hindered by a number of software and hardware limitations. The existing general-purpose hardware platforms used to accelerate DNNs are facing new challenges
Kamilya Smagulova +4 more
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Multi-engine packet classification hardware accelerator [PDF]
, 2009 As line rates increase, the task of designing high performance architectures with reduced power consumption for the processing of router traffic remains important. In this paper, we present a multi-engine packet classification hardware accelerator, which
Kennedy, Alan +3 more
core +1 more source
The GPU vs Phi Debate: Risk Analytics Using Many-Core Computing [PDF]
, 2015 The risk of reinsurance portfolios covering globally occurring natural catastrophes, such as earthquakes and hurricanes, is quantified by employing simulations.
Varghese, Blesson
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A High-Performance Multimem SHA-256 Accelerator for Society 5.0
IEEE Access, 2021 The development of a low-cost high-performance secure hash algorithm (SHA)-256 accelerator has recently received extensive interest because SHA-256 is important in widespread applications, such as cryptocurrencies, data security, data integrity, and ...
Thi Hong Tran +2 more
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Design of a BP neural network SoC based on domestic embedded CPU
Dianzi Jishu Yingyong, 2021 The paper designs a Back Propagation(BP)neural network system on chip(SoC) based on the domestic embedded Central Processing Unit(CPU) CK803S and its SoC design platform.
Xu Wenliang
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FPGA Implementation of A∗ Algorithm for Real-Time Path Planning
International Journal of Reconfigurable Computing, 2020 The traditional A∗ algorithm is time-consuming due to a large number of iteration operations to calculate the evaluation function and sort the OPEN list.
Yuzhi Zhou, Xi Jin, Tianqi Wang
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Alexandria Engineering Journal, 2022 Adoption of IoT technology without considering its security implications may expose network systems to a variety of security breaches. In network systems, IoT edge devices are a major source of security risks.
Atef Ibrahim, Fayez Gebali
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