Results 41 to 50 of about 77,762 (283)
Large Field-Size Throughput/Area Accelerator for Elliptic-Curve Point Multiplication on FPGA
Applied Sciences, 2023 This article presents a throughput/area accelerator for elliptic-curve point multiplication over GF(2571). To optimize the throughput, we proposed an efficient hardware accelerator architecture for a fully recursive Karatsuba multiplier to perform ...
Ahmed Alhomoud +5 more
doaj +1 more source
SPH Simulations with Reconfigurable Hardware Accelerator
, 2006 We present a novel approach to accelerate astrophysical hydrodynamical simulations. In astrophysical many-body simulations, GRAPE (GRAvity piPE) system has been widely used by many researchers.
Fukushige, T., Hamada, T., Nakasato, N.
core +2 more sources
Accelerating Fully Homomorphic Encryption in Hardware
IEEE Transactions on Computers, 2014 We present a custom architecture for realizing the Gentry-Halevi fully homomorphic encryption (FHE) scheme. This contribution presents the first full realization of FHE in hardware. The architecture features an optimized multi-million bit multiplier based on the Schonhage Strassen multiplication algorithm.
Doroez, Yarkin +2 more
openaire +3 more sources
A low-power, high-performance speech recognition accelerator [PDF]
, 2019 © 2019 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new ...
Arnau Montañés, José María +2 more
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Hardware Accelerated Power Estimation [PDF]
Design, Automation and Test in Europe, 2005 In this paper, we present power emulation, a novel design paradigm that utilizes hardware acceleration for the purpose of fast power estimation. Power emulation is based on the observation that the functions necessary for power estimation (power model evaluation, aggregation, etc.) can be implemented as hardware circuits.
Coburn, Joel +2 more
openaire +3 more sources
The Jefferson Lab 12 GeV Upgrade
, 2010 Construction of the 12 GeV upgrade to the Continuous Electron Beam Accelerator Facility (CEBAF) at the Thomas Jefferson National Accelerator Facility is presently underway.
McKeown, R. D.
core +2 more sources
Interstellar: Using Halide's Scheduling Language to Analyze DNN Accelerators
, 2020 We show that DNN accelerator micro-architectures and their program mappings represent specific choices of loop order and hardware parallelism for computing the seven nested loops of DNNs, which enables us to create a formal taxonomy of all existing dense
Bell, Steven Emberton +11 more
core +1 more source
Audio Denoising Coprocessor Based on RISC-V Custom Instruction Set Extension
Acoustics, 2022 As a typical active noise control algorithm, Filtered-x Least Mean Square (FxLMS) is widely used in the field of audio denoising. In this study, an audio denoising coprocessor based on Retrenched Injunction System Computer-V (RISC-V), a custom ...
Jun Yuan +5 more
doaj +1 more source
Hydra: An Accelerator for Real-Time Edge-Aware Permeability Filtering in 65nm CMOS
, 2017 Many modern video processing pipelines rely on edge-aware (EA) filtering methods. However, recent high-quality methods are challenging to run in real-time on embedded hardware due to their computational load. To this end, we propose an area-efficient and
Benini, Luca +6 more
core +1 more source
FEBS Open Bio, EarlyView.This protocol paper outlines methods to establish the success of a time‐resolved serial crystallographic experiment, by means of statistical analysis of timepoint data in reciprocal space and models in real space. We show how to amplify the signal from excited states to visualise structural changes in successful experiments.
Jake Hill +4 more
wiley +1 more source