Results 51 to 60 of about 77,762 (283)
Design of exact reduct rough set hardware accelerator for early-stage diabetes risk prediction
Diabetes is a prevalent, chronic metabolic disorder worldwide. Detecting and predicting risks early are vital for timely intervention. In this paper, the design and implementation of an Exact Reduct Rough Set Hardware Accelerator is presented for early ...
Kanchan S. Tiwari +6 more
doaj +1 more source
An Impulse-C Hardware Accelerator for Packet Classification Based on Fine/Coarse Grain Optimization
Current software-based packet classification algorithms exhibit relatively poor performance, prompting many researchers to concentrate on novel frameworks and architectures that employ both hardware and software components. The Packet Classification with
O. Ahmed +3 more
doaj +1 more source
Systemic sclerosis (SSc) is a rare autoimmune disease defined by immune dysregulation, vasculopathy, and progressive fibrosis of the skin and internal organs. Despite advances in care, major complications such as interstitial lung disease (ILD) and myocardial involvement remain the leading causes of morbidity and mortality.
Cristiana Sieiro Santos +2 more
wiley +1 more source
Binarized Convolutional Neural Networks with Separable Filters for Efficient Hardware Acceleration
State-of-the-art convolutional neural networks are enormously costly in both compute and memory, demanding massively parallel GPUs for execution. Such networks strain the computational capabilities and energy available to embedded and mobile processing ...
Gupta, Rajesh K. +6 more
core +1 more source
A Robust Adaptive One‐Sample‐Ahead Preview Super‐Twisting Sliding Mode Controller
Block Diagram of the Robust Adaptive One‐Sample‐Ahead Preview Super‐Twisting Sliding Mode Controller. ABSTRACT This article introduces a discrete‐time robust adaptive one‐sample‐ahead preview super‐twisting sliding mode controller. A stability analysis of the controller by Lyapunov criteria is developed to demonstrate its robustness in handling both ...
Guilherme Vieira Hollweg +5 more
wiley +1 more source
Novel CNN Accelerator Design With Dual Benes Network Architecture
We presented a novel hardware architecture that uses dual Benes networks to accelerate Convolutional Neural Network (CNN) algorithms. This architecture can reduce the need for high-speed buses and maintain a high-speed connection between execution units ...
Chun Yan Lo, Chiu-Wing Sham, Chong Fu
doaj +1 more source
A carbon‐free, as‐sintered MgO–steel cermet anode, fabricated via cold isostatic pressing using MgO–C refractory recyclate, was evaluated under laboratory‐scale K‐cryolite electrolysis at 800°C. Operation at this reduced temperature, combined with the electrolyte's limited electrical conductivity, led to an increase in cell voltage.
Farhan Hossain +7 more
wiley +1 more source
Video encoding based on novel HEVC standard is an extremely computationally expensive process and achieving efficient encoding requires intelligent utilization of all available resources, from both software and hardware perspective.
Igor Piljić, Leon Dragić, Mario Kovač
doaj +1 more source
Research on the design and optimization method of CNN accelerator based on HLS tools
Based on the idea of software and hardware co-design, this article uses HLS tools to design and implement a convolutional neural network accelerator on the PYNQ-Z2 platform, and uses the matrix cutting optimization method for convolution operations to ...
Cheng Jiafeng, Wang Hongliang
doaj +1 more source
Towards Defect Phase Diagrams: From Research Data Management to Automated Workflows
A research data management infrastructure is presented for the systematic integration of heterogeneous experimental and simulation data required for defect phase diagrams. The approach combines openBIS with a companion application for large‐object storage, automated metadata extraction, provenance tracking and federated data access, thereby supporting ...
Khalil Rejiba +5 more
wiley +1 more source

