Results 51 to 60 of about 717,844 (304)

All‐in‐One Analog AI Hardware: On‐Chip Training and Inference with Conductive‐Metal‐Oxide/HfOx ReRAM Devices

open access: yesAdvanced Functional Materials, EarlyView.
An all‐in‐one analog AI accelerator is presented, enabling on‐chip training, weight retention, and long‐term inference acceleration. It leverages a BEOL‐integrated CMO/HfOx ReRAM array with low‐voltage operation (<1.5 V), multi‐bit capability over 32 states, low programming noise (10 nS), and near‐ideal weight transfer.
Donato Francesco Falcone   +11 more
wiley   +1 more source

Hardware Accelerators in Autonomous Driving

open access: yesCoRR, 2023
Computing platforms in autonomous vehicles record large amounts of data from many sensors, process the data through machine learning models, and make decisions to ensure the vehicle's safe operation. Fast, accurate, and reliable decision-making is critical.
Ken Power   +4 more
openaire   +2 more sources

Optoelectronic Synaptic Devices Using Molecular Telluride Phase‐Change Inks for Three‐Factor Learning

open access: yesAdvanced Functional Materials, EarlyView.
Optoelectronic synaptic devices based on solution‐processed molecular telluride GST‐225 phase‐change inks are demonstrated for three‐factor learning. A global optical signal broadcast through a silicon waveguide induces non‐volatile conductance updates exclusively in locally electrically flagged memristors.
Kevin Portner   +14 more
wiley   +1 more source

Novel CNN Accelerator Design With Dual Benes Network Architecture

open access: yesIEEE Access, 2023
We presented a novel hardware architecture that uses dual Benes networks to accelerate Convolutional Neural Network (CNN) algorithms. This architecture can reduce the need for high-speed buses and maintain a high-speed connection between execution units ...
Chun Yan Lo, Chiu-Wing Sham, Chong Fu
doaj   +1 more source

Accelerating FrodoKEM in Hardware

open access: yesIACR Transactions on Cryptographic Hardware and Embedded Systems
FrodoKEM, a conservative post-quantum key encapsulation mechanism based on the plain Learning with Errors (LWE) problem, has been recommended for use by several government cybersecurity agencies and is currently undergoing standardization by the International Organization for Standardization (ISO).
Sanjay Deshpande   +2 more
openaire   +2 more sources

Extension Module for Application-Specific Hardware on the Minirobot Khepera [PDF]

open access: yes, 2001
Niemann J-C, Witkowski U, Porrmann M, Rückert U. Extension Module for Application-Specific Hardware on the Minirobot Khepera. In: Autonomous Minirobots for Research and Edutainment (AMiRE 2001).
Porrmann, Mario ; https://orcid.org/   +3 more
core  

Multimode Oxide‐Based Optoelectronic Memtransistor for In‐Sensor Vision Processing

open access: yesAdvanced Functional Materials, EarlyView.
A multimode optoelectronic memtransistor (OEMT) is demonstrated for vision explainable artificial intelligence (VXAI) hardware. By integrating optical sensing, electrical masking, and non‐volatile memory, the device enables key operations required for generating saliency information.
Min Gu Lee   +10 more
wiley   +1 more source

Performance-efficient integration and programming approach of DCT accelerator for HEVC in MANGO platform

open access: yesAutomatika, 2019
Video encoding based on novel HEVC standard is an extremely computationally expensive process and achieving efficient encoding requires intelligent utilization of all available resources, from both software and hardware perspective.
Igor Piljić, Leon Dragić, Mario Kovač
doaj   +1 more source

Deep Learning Accelerators’ Configuration Space Exploration Effect on Performance and Resource Utilization: A Gemmini Case Study

open access: yesSensors, 2023
Though custom deep learning (DL) hardware accelerators are attractive for making inferences in edge computing devices, their design and implementation remain a challenge. Open-source frameworks exist for exploring DL hardware accelerators.
Dennis Agyemanh Nana Gookyi   +4 more
doaj   +1 more source

Energy efficient packet classification hardware accelerator [PDF]

open access: yes, 2008
Packet classification is an important function in a router's line-card. Although many excellent solutions have been proposed in the past, implementing high speed packet classification reaching up to OC-192 and even OC-768 with reduced cost and low power ...
Wang, Xiaojun   +5 more
core   +2 more sources

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