Results 61 to 70 of about 717,844 (304)
This review revisits optoelectronic neuromorphic devices that extend from unimodal sensing toward multimodal perception. Five types of stimuli‐to‐output information flow that are classified based on the device roles within the system and applications are summarized and discussed.
Jihyun Shin +6 more
wiley +1 more source
Possibilities of using of hardware accelerators for intrusion detection and prevention systems
The subject of this study is the capabilities of FPGA technology for cybersecurity solutions with the network interface accelerators of SmartNIC, as well as the technologies for building, deploying, supporting, and accelerating intrusion detection ...
Artem Tetskyi, Artem Perepelitsyn
doaj +1 more source
Research on the design and optimization method of CNN accelerator based on HLS tools
Based on the idea of software and hardware co-design, this article uses HLS tools to design and implement a convolutional neural network accelerator on the PYNQ-Z2 platform, and uses the matrix cutting optimization method for convolution operations to ...
Cheng Jiafeng, Wang Hongliang
doaj +1 more source
AbstractWith Moore’s law and Dennard’s scaling no longer fueling the improvement in computing performance, new avenues for increasing performance are needed. Hardware acceleration is one avenue where many researchers and industrial parties are working and investing.
openaire +1 more source
Memristive‐Gated RC‐Delay Synaptic Transistors for Time‐Encoded Analog in‐Memory Computing
A Memristive‐Gated Transistor for Time‐Encoded Analog In‐Memory Computing — By exploiting the RC delay of a self‐rectifying interface‐type memristor, nonlinear I–V distortion is structurally bypassed, enabling 3‐bit nonvolatile memory, spike‐timing‐based analog encoding, and hardware‐calibrated reservoir‐computing validation within a unified device ...
Yun‐Seo Shin +7 more
wiley +1 more source
Objectives. The growing demand for higher computational performance and energy efficiency has motivated the increasing adoption of specialized heterogeneous computing systems incorporating hardware accelerators with massive parallelism.
A. S. Zuev +2 more
doaj +1 more source
A compression strategy to accelerate LSTM meta-learning on FPGA
Driven by edge computing, how to efficiently deploy the meta-learner LSTM in the resource constrained FPGA terminal equipment has become a big problem.
NianYi Wang +4 more
doaj +1 more source
Implementation of artificial neural networks on a reconfigurable hardware accelerator
Porrmann M, Witkowski U, Kalte H, Rückert U. Implementation of artificial neural networks on a reconfigurable hardware accelerator. In: Parallel, Distributed and Network-based Processing, 2002. Proceedings. 10th Euromicro Workshop on. IEEE Comput. Soc;
Witkowski, U. +7 more
core +1 more source
Understanding and Mitigating Hardware Failures in Deep Learning Training Accelerator Systems
<p>This is the artifact repo for paper Understanding and Mitigating Hardware Failures in Deep Learning Training Accelerator Systems.</p ...
He, Yi
core +1 more source
The physical realization of artificial neurons is a critical challenge for energy‐efficient neuromorphic computing. This review presents a comprehensive analysis of the evolution of artificial neuron implementations from conventional CMOS to emerging post‐CMOS technologies.
Kannan Udaya Mohanan +4 more
wiley +1 more source

