Results 111 to 120 of about 717,844 (304)
Path‐decoupled III–V van der Waals memtransistors spatially separate ionic and electronic transport to overcome the conventional trade‐off between accuracy and energy in neuromorphic hardware. Mobile K+ ions in the vdW gaps set a wide conductance window, Gmax/Gmin, while gate‐tunable hole conduction lowers programming energy, enabling reliable ...
Jihong Bae +13 more
wiley +1 more source
Self‐invalidating multilayer physical unclonable functions (PUFs) integrate fingerprint‐like metal nanopattern bilayers from block copolymer templates with highly reactive reduced graphene oxide (rGO) interlayers. This tamper‐responsive architecture blocks all unauthorized physical and chemical replication attempts while autonomously deactivating ...
Gyu Hui Jo +7 more
wiley +1 more source
A Multiplier-Free Convolution Neural Network Hardware Accelerator for Real-Time Bearing Condition Detection of CNC Machinery. [PDF]
Liang YP, Hung MY, Chung CC.
europepmc +1 more source
Seamless Mechanical Programming Through Hybrid Epoxy–Acrylate Printing for Soft–Rigid Robots
Hybrid epoxy‐acrylate printing enables seamless fabrication of soft–rigid robotic systems with covalently integrated interfaces and functionally graded mechanics. Grayscale exposure expands the accessible material space, enabling spatially programmed actuation through patterned stiffness while revealing the mechanics and durability of continuously ...
David C. Bershadsky +3 more
wiley +1 more source
Hardware accelerator for the JPEG encoder on the xilinx SPARTAN 3 FPGA [PDF]
textThe report detailing the Hardware Accelerator for the JPEG encoder is organized into three sections. First, it will review the processes of the Joint Photographic Experts Group (JPEG) encoding and decoding standard.
Zheng, Feng, M.S. in Engineering
core +1 more source
Understanding the 6-dimensional phase space distribution of particle beams is essential for optimizing accelerator performance. Conventional diagnostics such as use of transverse deflecting cavities offer detailed characterization but require dedicated ...
Seongyeol Kim +9 more
doaj +1 more source
Designing Deep Learning Hardware Accelerator and Efficiency Evaluation. [PDF]
Qi Z, Chen W, Naqvi RA, Siddique K.
europepmc +1 more source
Hardware accelerator design for image processing
This paper proposed an image processing system based on hardware accelerator design method in FPGA chip. The architectures of the image system will be described.
Li, Shih-An +6 more
core +1 more source
The NVIDIA Deep Learning Accelerator (NVDLA) is a free and open architecture that aims at promoting a standard way of designing deep neural network (DNN) inference engines.
Bertozzi D. +5 more
core +1 more source
Nonplanar Bouligand Architectures for Enhanced Mechanical Performance in Cementitious Composites
Inspired by the impact region of the Mantis shrimp dactyl club, nonplanar additive manufacturing translates sinusoidal Bouligand architectures into cementitious composites. Printing‐induced anisotropy and architected interfaces promote distributed damage and arrest crack propagation, enhancing strength and energy absorption.
Yu Wang +7 more
wiley +1 more source

