Results 1 to 10 of about 81,345 (118)
A SHA-256 Hybrid-Redundancy Hardware Architecture for Detecting and Correcting Errors [PDF]
Sensors, 2022 In emergent technologies, data integrity is critical for message-passing communications, where security measures and validations must be considered to prevent the entrance of invalid data, detect errors in transmissions, and prevent data loss.
Ignacio Algredo-Badillo +5 more
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Synthesis Optimization of Arithmetic Circuits on Coarse-Grain Reconfigurable Architecture [PDF]
مجله مدل سازی در مهندسی, 2022 The increasing capabilities of integrated circuits and the complexity of applications have led hardware design methods and tools to higher levels of abstraction. High-level synthesis is one of the key steps in increasing the level of abstraction, and the
Samaneh Emami +2 more
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Area-Time Efficient Hardware Architecture for CRYSTALS-Kyber
Applied Sciences, 2022 This paper presents a novel area-time efficient hardware architecture of the lattice-based CRYSTALS-Kyber, which has entered the third round of the post-quantum cryptography standardization competition hosted by the National Institute of Standards and ...
Tuy Tan Nguyen +3 more
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Journal of Low Power Electronics and Applications, 2021 In embedded applications that use neural networks (NNs) for classification tasks, it is important to not only minimize the power consumption of the NN calculation, but of the whole system.
Daniel Reiser +8 more
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Hardware Architecture for Reducing Worst-Case Latency in Fast SCF Polar Decoders
IEEE Access, 2023 The Successive Cancellation Flip (SCF)-based decoding for polar codes requires significant latency at low SNRs. This paper proposes a low-latency SCF-based decoding and decoder architecture based on decoding history.
Useok Lee +2 more
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IEEE Access, 2023 Embedded stereo vision systems based on traditional approaches often require a disparity refinement process to enhance image quality. Weighted median filter (WMF)-based processors are commonly employed for their excellent refinement performance. However,
Cheol-Ho Choi +3 more
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Real-Time Energy Efficient Hand Pose Estimation: A Case Study
Sensors, 2020 The estimation of human hand pose has become the basis for many vital applications where the user depends mainly on the hand pose as a system input. Virtual reality (VR) headset, shadow dexterous hand and in-air signature verification are a few examples ...
Mhd Rashed Al Koutayni +7 more
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Mathematics, 2022 In this paper, the conceptualization of a control hardware architecture aimed to the implementation of integer- and fractional-order identification and control algorithms is presented.
Juan J. Gude, Pablo García Bringas
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A Hardware Architecture of a Counter-Based Entropy Coder [PDF]
ITB Journal of Engineering Science, 2012 This paper describes a hardware architectural design of a real-time counter based entropy coder at a register transfer level (RTL) computing model. The architecture is based on a lossless compression algorithm called Rice coding, which is optimal for an ...
Armein Z R Langi
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iScience, 2022 Summary: Memristor-based Pavlov associative memory circuit presented today only realizes the simple condition reflex process. The secondary condition reflex endows the simple condition reflex process with more bionic, but it is only demonstrated in ...
Guangdong Zhou +11 more
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