Results 21 to 30 of about 2,650,279 (206)

Configurable Encryption and Decryption Architectures for CKKS-Based Homomorphic Encryption

Sensors, 2023
With the increasing number of edge devices connecting to the cloud for storage and analysis, concerns about security and data privacy have become more prominent.
Jaehyeok Lee, Phap Ngoc Duong, Hanho Lee
doaj   +1 more source

iDocChip: A Configurable Hardware Accelerator for an End-to-End Historical Document Image Processing

Journal of Imaging, 2021
In recent years, there has been an increasing demand to digitize and electronically access historical records. Optical character recognition (OCR) is typically applied to scanned historical archives to transcribe them from document images into machine ...
Menbere Kina Tekleyohannes, Vladimir Rybalkin, Muhammad Mohsin Ghaffar, Javier Alejandro Varela, Norbert Wehn, Andreas Dengel   +5 more
doaj   +1 more source

An efficient hardware architecture for a neural network activation function generator [PDF]

, 2006
This paper proposes an efficient hardware architecture for a function generator suitable for an artificial neural network (ANN). A spline-based approximation function is designed that provides a good trade-off between accuracy and silicon area, whilst ...
Daniel Larkin, O'Connor, Noel E., Valentin Muresan, Larkin, Daniel, Andrew Kinane, O\u27Connor, Noel E., Muresan, Valentin, Noel O’Connor, Kinane, Andrew   +8 more
core   +2 more sources

Zig-Zag Based Single-Pass Connected Components Analysis

Journal of Imaging, 2019
Single-pass connected components analysis (CCA) algorithms suffer from a time overhead to resolve labels at the end of each image row. This work demonstrates how this overhead can be eliminated by replacing the conventional raster scan by a zig-zag scan.
Donald G. Bailey, Michael J. Klaiber
doaj   +1 more source

A 181 GOPS AKAZE Accelerator Employing Discrete-Time Cellular Neural Networks for Real-Time Feature Extraction

Sensors, 2015
This paper proposes a real-time feature extraction VLSI architecture for high-resolution images based on the accelerated KAZE algorithm. Firstly, a new system architecture is proposed.
Guangli Jiang, Leibo Liu, Wenping Zhu, Shouyi Yin, Shaojun Wei   +4 more
doaj   +1 more source

Hardware Architecture of Stochastic Computing Neural Network

Jisuanji kexue yu tansuo, 2021
Stochastic computing is a kind of logic calculation that converts binary into probabilistic coded digital pulse stream. At the cost of computing power and time delay, it has the computing advantages of low power consumption and high energy efficiency. In
CHEN Yuhao, SONG Yinjie, ZHU Yanan, GAO Yunfei, LI Hongge+
doaj   +1 more source

TRUSS: A Reliable, Scalable Server Architecture [PDF]

, 2005
Traditional techniques that mainframes use to increase reliability special hardware or custom software - are incompatible with commodity server requirements.
Kim, J, Nowatzyk, AG, Nurvitadhi, E, Hoe, JC, Smolens, JC, Chung, ES, Liaskovitis, V, Gold, BT, Falsafi, B, V. Liaskovitis, A.G. Nowatzyk, B. Falsafi, E. Nurvitadhi, J.C. Hoe, J.C. Smolens, B.T. Gold, Jangwoo Kim, E.S. Chung   +17 more
core   +1 more source

Cloud Computing and Business Intelligence [PDF]

Database Systems Journal, 2015
The complexity of data resulting from business process is becoming overwhelming for the systems that don't use shared resources. Many aspects of the business process must be recorded and analysed in a short period of time with no errors at all.
Alexandru Adrian TOLE
doaj  

An Accelerator Design Using a MTCA Decomposition Algorithm for CNNs

Sensors, 2020
Due to the high throughput and high computing capability of convolutional neural networks (CNNs), researchers are paying increasing attention to the design of CNNs hardware accelerator architecture. Accordingly, in this paper, we propose a block parallel
Yunping Zhao, Jianzhuang Lu, Xiaowen Chen   +2 more
doaj   +1 more source

A Real-Time Naive Bayes Classifier Accelerator on FPGA

IEEE Access, 2020
In this paper, we propose a real-time hardware naive Bayes classifier (NBC) which is implemented on field programmable gate array (FPGA). We first use logarithm transformation based look-up table and float-to-fixed point process to simplify the ...
Zhen Xue, Jizeng Wei, Wei Guo
doaj   +1 more source