Results 31 to 40 of about 2,650,279 (206)
IEEE Access, 2022 Aiming at providing an efficient hardware architecture for generalized spatial modulation (GSM) multiple-input multiple-output (MIMO) systems, in this paper a COordinate Rotation DIgital Computer (CORDIC) -based symbol detector is proposed.
Hoang-Yang Lu +5 more
doaj +1 more source
Efficient Phase Unwrapping Architecture for Digital Holographic Microscopy
Sensors, 2011 This paper presents a novel phase unwrapping architecture for accelerating the computational speed of digital holographic microscopy (DHM). A fast Fourier transform (FFT) based phase unwrapping algorithm providing a minimum squared error solution is ...
Wen-Jyi Hwang +2 more
doaj +1 more source
A Memory-Efficient Hardware Architecture for a Pulse Doppler Radar Vehicle Detector
, 2011 In this paper, we propose a memory-efficient structure for a pulse Doppler radar in order to reduce the hardware's complexity. The conventional pulse Doppler radar is computed by fast frequency transform (FFT) of all range cells in order to extract ...
Kim, Sang-Dong +3 more
core +1 more source
Parallel hardware architecture.
, 2019 Parallel hardware architecture.
Saeed ur Rehman (7252388) +3 more
core +1 more source
A low complexity hardware architecture for motion estimation [PDF]
, 2006 This paper tackles the problem of accelerating motion estimation for video processing. A novel architecture using binary data is proposed, which attempts to reduce power consumption.
O'Connor, Noel E. +6 more
core +2 more sources
Mechanisms for Parallelism Specialization for the DySER Architecture [PDF]
, 2012 Specialization is a promising direction for improving processor energy efficiency. With functionality specialization, hardware is designed for application-specific units of computation.
Ho, Chen-Han +3 more
core
Efficient hardware architectures for MPEG-4 core profile [PDF]
, 2005 Efficient hardware acceleration architectures are proposed for the most demandingMPEG-4 core profile algorithms, namely; texture motion estimation (TME), binary motion estimation (BME)and the shape adaptive discrete cosine transform (SA-DCT).
O'Connor, Noel E. +3 more
core +2 more sources
A Lightweight System-On-Chip Based Cryptographic Core for Low-Cost Devices
Sensors, 2022 The backbone of the Internet of things (IoT) platform consists of tiny low-cost devices that are continuously exchanging data. These devices are usually limited in terms of hardware footprint, memory capacity, and processing power.
Dennis Agyemanh Nana Gookyi +1 more
doaj +1 more source
Hardware architecture template diagram.
, 2019 Hardware architecture template diagram.
Chaoguang Men (7484843) +4 more
core +1 more source
An Area-Time Efficient Hardware Architecture for ML-KEM Post-Quantum Cryptography Standard
IEEE AccessTo facilitate the integration of the NIST-standardized post-quantum cryptographic (PQC) algorithm, Module Lattice-based Key Encapsulation Mechanism (ML-KEM), into quantum-resistant devices and cryptosystems, this study introduces an area-time efficient ...
Trong-Hung Nguyen +6 more
doaj +1 more source